http://blog.ektel.com.np ektel communication system Sat, 21 Apr 2012 09:52:50 +0000 en hourly 1 http://wordpress.org/?v=3.3.1 Telecommunication Entropy http://blog.ektel.com.np/2012/04/telecommunication-entropy/?utm_source=rss&utm_medium=rss&utm_campaign=telecommunication-entropy http://blog.ektel.com.np/2012/04/telecommunication-entropy/#comments Sat, 21 Apr 2012 05:54:18 +0000 admin http://blog.ektel.com.np/?p=375 Telecommunication Entropy can be regarded as the fundamental unit of information that is being transferred, received and/or stored with the passage of time. The information being transferred or received as electromagnetic waves having both wave and particle and stored in electronic circuits as charges by virtual of transistor capacitor or gate capacitance such as RAM and ROM devices. There is also flow of the stored charges on the huge number of transistors and gates and it is being conceived by us as data flow between the electronic circuits. Such signal manipulation is done and studied under DSP(Digital Signal Processing) which involves their analysis and research.

Entropy itself is probabilistic in nature. Self information is measure of occurrence of the quantized amplitude during quantization process. Say an amplitude of 4Volt occurred 3 times(frequency) then the self information would be log(1/3) in base 1o. Mutual Entropy is the total aggregated self information of the  possible sample space of any number of samples taken randomly from the information source. The information source is transducers such as antenna that captures frequency of electromagnetic waves when incident on it and converts that energy of the wave to equivalent proportional voltage signal. This voltage signal is quantized, source encoded, channel encoded and modulated before sending them out again out to the air or space.

]]> http://blog.ektel.com.np/2012/04/telecommunication-entropy/feed/ 0 Huffman encoder decoder VLSI design Systematic Block Diagram http://blog.ektel.com.np/2012/04/huffman-encoder-decoder-vlsi-design-systematic-block-diagram/?utm_source=rss&utm_medium=rss&utm_campaign=huffman-encoder-decoder-vlsi-design-systematic-block-diagram http://blog.ektel.com.np/2012/04/huffman-encoder-decoder-vlsi-design-systematic-block-diagram/#comments Fri, 20 Apr 2012 02:51:59 +0000 admin http://blog.ektel.com.np/?p=347 Note: Click the picture below to understand clearly

The picture below shows the huffman encoder decoder vlsi design systematic block diagram using the verilog HDL or VHDL codes and implemented on Xilinx ISE software.

About the picture:

This is a block diagram showing Huffman Encoder/ Decoder VLSI implemented block diagram. Huffman encoders decoders are source encoder decoder that are widely used in image and video compression. The circuit above has gates within it (shown below) that actually performs Huffman algorithm calculation and is based on concept of compactization of bits to lower the entropy without any actual loss of bits. Compactization of bits means compression. Say 10 bits/symbol is the initial entropy of image or a frame of video signal. The signal content of these(image,video frame) is spread out in space in such a way that most of real content of image that we require(for distinguishing objects) occupies less space than the space of the captured image or video frame. This is because units of signals in time does not does not seem to occur or born out in a random manner but in some deterministic manner since some units occur frequently and some unit occur less frequently, that is , probabilistic nature. In other words, if you had only the signal information(frequency spectrum) of the real content then you could store, transmit and upon unfolding the real content you would see the exact image or video signal. There is no loss of information just compactization of units based on probabilistic nature of occurrence of information units. Hence, it is known as Lossless compression and related to the Shanon Paper on Entropy and Source coding.  Hence source encoding means the reduce the redundancy(Captured space - Compacted Captured Space) contained with the captured space of image or video frame. Hence, source encoding is also known as removing redundancy in direct correspondence to channel encoding which is also known as adding redundancy. Meaning first, reduce(compress) redundant signal content at the source encoder and second add redundant signal content to the output from source encoder.

Huffman systematic VHDL block diagram

Fig: Huffman systematic VHDL block diagram

 

Gate Level:

The picture below shows the gate level of the same chip level block diagram above. Shown in the pictures are logic units and functional components(adder, subtractor, multiplexers, shifters, counters etc), input and output ports and interconnection between all the elements that makes up the VLSI huffman encoder, decoder. This is from Xilinx software.

Huffman encoder gate level diagram

Fig: Huffman encoder gate level diagram

Source encoder gate level diagram

Fig: Source encoder gate level diagram

Huffman compression gate level diagram

Fig: Huffman compression gate level diagram

VLSI design gate level diagram

Fig: VLSI design gate level diagram

You can read more below:

 

]]> http://blog.ektel.com.np/2012/04/huffman-encoder-decoder-vlsi-design-systematic-block-diagram/feed/ 0 Huffman Encoder VHDL code http://blog.ektel.com.np/2012/04/huffman-encoder-vhdl-code/?utm_source=rss&utm_medium=rss&utm_campaign=huffman-encoder-vhdl-code http://blog.ektel.com.np/2012/04/huffman-encoder-vhdl-code/#comments Fri, 20 Apr 2012 01:48:55 +0000 admin http://blog.ektel.com.np/?p=344 library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

ENTITY huffman_en IS
PORT (
CLK                     : IN std_logic;
RST                     : IN std_logic;
rdy_in                  : IN std_logic;
rl_in                   : IN std_logic_vector(17 DOWNTO 0);
dc_in                   : IN std_logic_vector(11 DOWNTO 0);
scan_type               : IN std_logic;
luma                    : IN std_logic;
huffman_out             : OUT std_logic_vector(15 DOWNTO 0);
eob                     : IN std_logic;
rdy_out                 : OUT std_logic);
END huffman_en;

ARCHITECTURE translated OF huffman_en IS

-- signals
SIGNAL cntr64                   :  std_logic_vector(6 DOWNTO 0);
SIGNAL cl_sum_rdy               :  std_logic;
SIGNAL size                     :  std_logic_vector(3 DOWNTO 0);
SIGNAL cl_sum                   :  std_logic_vector(5 DOWNTO 0);
SIGNAL cl_sum_prev              :  std_logic_vector(5 DOWNTO 0);
SIGNAL codelength_dc            :  std_logic_vector(3 DOWNTO 0);
SIGNAL codelength_ac            :  std_logic_vector(4 DOWNTO 0);
SIGNAL codelength1              :  std_logic_vector(4 DOWNTO 0);
SIGNAL codelength2              :  std_logic_vector(4 DOWNTO 0);
SIGNAL codelength_ac1           :  std_logic_vector(4 DOWNTO 0);
SIGNAL vlcode_dc                :  std_logic_vector(9 DOWNTO 0);
SIGNAL vlcode1                  :  std_logic_vector(17 DOWNTO 0);
SIGNAL vlcode2                  :  std_logic_vector(17 DOWNTO 0);
SIGNAL vlcode3                  :  std_logic_vector(17 DOWNTO 0);
SIGNAL vlcode4                  :  std_logic_vector(17 DOWNTO 0);
SIGNAL vlcode_ac1               :  std_logic_vector(17 DOWNTO 0);
SIGNAL vlcode_ac                :  std_logic_vector(17 DOWNTO 0);
SIGNAL cl_sum_shift             :  std_logic_vector(38 DOWNTO 0);
SIGNAL full_flag1               :  std_logic;
SIGNAL half_flag1               :  std_logic;
SIGNAL half_flag2               :  std_logic;
SIGNAL full_flag2               :  std_logic;
SIGNAL half_flag3               :  std_logic;
SIGNAL full_flag3               :  std_logic;
SIGNAL full_flag4               :  std_logic;
SIGNAL half_flag4               :  std_logic;
SIGNAL full_flag5               :  std_logic;
SIGNAL full_flag6               :  std_logic;
SIGNAL half_flag5               :  std_logic;
SIGNAL mult_out                 :  std_logic_vector(38 DOWNTO 0);
SIGNAL mult_out_int                 :  std_logic_vector(56 DOWNTO 0);
SIGNAL upper_reg1               :  std_logic_vector(16 DOWNTO 1);
SIGNAL middle_reg1              :  std_logic_vector(16 DOWNTO 1);
SIGNAL lower_reg1               :  std_logic_vector(16 DOWNTO 1);
SIGNAL upper_reg2               :  std_logic_vector(16 DOWNTO 1);
SIGNAL middle_reg2              :  std_logic_vector(16 DOWNTO 1);
SIGNAL middle_reg3              :  std_logic_vector(16 DOWNTO 1);

SIGNAL temp4,temp5              :  std_logic_vector(11 DOWNTO 0);
SIGNAL temp6,temp7              :  std_logic_vector(11 DOWNTO 0);
SIGNAL temp8,temp9              :  std_logic_vector(11 DOWNTO 0);
SIGNAL temp10                   :  std_logic_vector(17 DOWNTO 0);
SIGNAL temp11                   :  std_logic_vector(1 DOWNTO 0);

BEGIN

--***************************************************************************
-- Find the size for the "Differential_DC" value. The differential_dc_size gives the number of
--  Find the size for the "Differential_DC" value. The differential_dc_size gives the number of
-- bits to be used to denote the DC_difference value. ram_dc_diff . Table 1 in document

--   PROCESS (CLK)
--   BEGIN
--      IF (CLK'EVENT AND CLK = '1') THEN
--         CASE dc_in IS
--         WHEN "111111111111" => size <= "0001";
--         WHEN "11111111110-" => size <= "0010";
--         WHEN "1111111110--" => size <= "0011";
--         WHEN "111111110---" => size <= "0100";
--         WHEN "11111110----" => size <= "0101";
--         WHEN "1111110-----" => size <= "0110";
--         WHEN "111110------" => size <= "0111";
--         WHEN "11110-------" => size <= "1000";
--         WHEN "1110--------" => size <= "1001";
--         WHEN "110---------" => size <= "1010";
--         WHEN "10----------" => size <= "1011";
--         WHEN "000000000000" => size <= "0000";
--         WHEN "000000000001" => size <= "0001";
--         WHEN "00000000001-" => size <= "0010";
--         WHEN "0000000001--" => size <= "0011";
--         WHEN "000000001---" => size <= "0100";
--         WHEN "00000001----" => size <= "0101";
--         WHEN "0000001-----" => size <= "0110";
--         WHEN "000001------" => size <= "0111";
--         WHEN "00001-------" => size <= "1000";
--         WHEN "0001--------" => size <= "1001";
--         WHEN "001---------" => size <= "1010";
--         WHEN "01----------" => size <= "1011";
--         WHEN OTHERS => size <= "0000";
--         END CASE;
--      END IF;
--   END PROCESS;

PROCESS (CLK)
VARIABLE size_temp  : std_logic_vector(3 DOWNTO 0);
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (std_match(dc_in, "111111111111")) THEN
size_temp := "0001";
ELSIF (std_match(dc_in, "11111111110-")) THEN
size_temp := "0010";
ELSIF (std_match(dc_in, "1111111110--")) THEN
size_temp := "0011";
ELSIF (std_match(dc_in, "111111110---")) THEN
size_temp := "0100";
ELSIF (std_match(dc_in, "11111110----")) THEN
size_temp := "0101";
ELSIF (std_match(dc_in, "1111110-----")) THEN
size_temp := "0110";
ELSIF (std_match(dc_in, "111110------")) THEN
size_temp := "0111";
ELSIF (std_match(dc_in, "11110-------")) THEN
size_temp := "1000";
ELSIF (std_match(dc_in, "1110--------")) THEN
size_temp := "1001";
ELSIF (std_match(dc_in, "110---------")) THEN
size_temp := "1010";
ELSIF (std_match(dc_in, "10----------")) THEN
size_temp := "1011";
ELSIF (std_match(dc_in, "000000000000")) THEN
size_temp := "0000";
ELSIF (std_match(dc_in, "000000000001")) THEN
size_temp := "0001";
ELSIF (std_match(dc_in, "00000000001-")) THEN
size_temp := "0010";
ELSIF (std_match(dc_in, "0000000001--")) THEN
size_temp := "0011";
ELSIF (std_match(dc_in, "000000001---")) THEN
size_temp := "0100";
ELSIF (std_match(dc_in, "00000001----")) THEN
size_temp := "0101";
ELSIF (std_match(dc_in, "0000001-----")) THEN
size_temp := "0110";
ELSIF (std_match(dc_in, "000001------")) THEN
size_temp := "0111";
ELSIF (std_match(dc_in, "00001-------")) THEN
size_temp := "1000";
ELSIF (std_match(dc_in, "0001--------")) THEN
size_temp := "1001";
ELSIF (std_match(dc_in, "001---------")) THEN
size_temp := "1010";
ELSIF (std_match(dc_in, "01----------")) THEN
size_temp := "1011";
ELSE
size_temp := "0000";

END IF;
END IF;
size <= size_temp;
END PROCESS;

--***************************************************************************
-- variable length code and the corresponding code length for DC_Differential
-- After finding the size of the DC_Differential, the variable length code used to denote it is found.
--  After finding the size of the DC_Differential, the variable length code used to denote it is found.
-- For example, if the size is 10, 10 bits are used to denote the dc_differential value and a variable
-- length code prefix of "111111110" is used along with the 10 bit value.

-- luma = 1'b1 denotes a luminance block and lume = 1'b0 denotes a chrominance block
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (RST = '1') THEN
vlcode_dc <= "0000000000";
codelength_dc <= "0000";
ELSE
IF (cntr64 = "0000001") THEN
CASE luma IS
WHEN '1' =>
CASE size IS --ram_dc_size1
WHEN "0000" => vlcode_dc <= "0000000100"; codelength_dc <= "0011";
WHEN "0001" => vlcode_dc <= "0000000000"; codelength_dc <= "0010";
WHEN "0010" => vlcode_dc <= "0000000001"; codelength_dc <= "0010";
WHEN "0011" => vlcode_dc <= "0000000101"; codelength_dc <= "0011";
WHEN "0100" => vlcode_dc <= "0000000110"; codelength_dc <= "0011";
WHEN "0101" => vlcode_dc <= "0000001110"; codelength_dc <= "0100";
WHEN "0110" => vlcode_dc <= "0000011110"; codelength_dc <= "0101";
WHEN "0111" => vlcode_dc <= "0000111110"; codelength_dc <= "0110";
WHEN "1000" => vlcode_dc <= "0001111110"; codelength_dc <= "0111";
WHEN "1001" => vlcode_dc <= "0011111110"; codelength_dc <= "1000";
WHEN "1010" => vlcode_dc <= "0111111110"; codelength_dc <= "1001";
WHEN "1011" => vlcode_dc <= "0111111111"; codelength_dc <= "1001";
WHEN OTHERS => vlcode_dc <= "0000000000"; codelength_dc <= "0000";
END CASE;
WHEN '0' =>
CASE size IS --ram_dc_size2
WHEN "0000" => vlcode_dc <= "0000000000"; codelength_dc <= "0010";
WHEN "0001" => vlcode_dc <= "0000000001"; codelength_dc <= "0010";
WHEN "0010" => vlcode_dc <= "0000000010"; codelength_dc <= "0010";
WHEN "0011" => vlcode_dc <= "0000000110"; codelength_dc <= "0011";
WHEN "0100" => vlcode_dc <= "0000001110"; codelength_dc <= "0100";
WHEN "0101" => vlcode_dc <= "0000011110"; codelength_dc <= "0101";
WHEN "0110" => vlcode_dc <= "0000111110"; codelength_dc <= "0110";
WHEN "0111" => vlcode_dc <= "0001111110"; codelength_dc <= "0111";
WHEN "1000" => vlcode_dc <= "0011111110"; codelength_dc <= "1000";
WHEN "1001" => vlcode_dc <= "0111111110"; codelength_dc <= "1001";
WHEN "1010" => vlcode_dc <= "1111111110"; codelength_dc <= "1010";
WHEN "1011" => vlcode_dc <= "1111111111"; codelength_dc <= "1010";
WHEN OTHERS => vlcode_dc <= "0000000000"; codelength_dc <= "0000";
END CASE;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END IF;
END PROCESS;

--***************************************************************************
-- variable length code and corresponding code length for AC coefficients.
--  variable length code and corresponding code length for AC coefficients.
--    Table zero is used for intra blocks anf table one is used for non-intra
--    blocks.  For a run/level pair not defined in table zero or one, an escape
--    code followed by a 6 bit run symbol and 12 bit level is used.

--assign run_level_pair <= {run_in,level_in};

--always @ (posedge CLK)
-- always @ (posedge CLK)
-- begin
--   if (RST)
--      begin vlcode_ac1 <= {18'b0}; codelength_ac1 <= 5'd0; end
--   else
-- begin if (rdy_in == 1'b1)
-- begin
-- case(rl_in)
--         18'b000000000000000001:
--            begin  vlcode_ac1 <= {17'b00000000000001010,rl_in[11]}; codelength_ac1 <= 5'd5; end
--         18'b000000000000000101:
--            begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd4; end
--         18'b000000000000001010:
--            begin  vlcode_ac1 <= {17'b00000000000001110,rl_in[11]}; codelength_ac1 <= 5'd5; end
--         18'b000001000000000101:
--            begin  vlcode_ac1 <= {18'b111100001111001101}; codelength_ac1 <= 5'd18; end
--         18'b000011000000000111:
--            begin  vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd6; end
--       18'b000111000000001001:
--            begin  vlcode_ac1 <= {17'b00000000000000000,rl_in[11]}; codelength_ac1 <= 5'd5; end
--       18'b010000000000010000:
--            begin  vlcode_ac1 <= {17'b10000000000010110,rl_in[11]}; codelength_ac1 <= 5'd7; end
--       18'b010101000000001001:
--            begin  vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd7; end
--     default:
--            begin  vlcode_ac1 <= {18'b111111111111111111}; codelength_ac1 <= 5'd18; end
-- endcase
-- end
-- end
-- end

--***************************************************************************

temp4 <= '0' & rl_in(10 DOWNTO 0);
temp5 <= '0' & rl_in(10 DOWNTO 0);
temp6 <= '0' & rl_in(10 DOWNTO 0);
temp7 <= '0' & rl_in(10 DOWNTO 0);
temp8 <= '0' & rl_in(10 DOWNTO 0);
temp9 <= '0' & rl_in(10 DOWNTO 0);
temp10 <= scan_type & rl_in(17 DOWNTO 12) &  rl_in(10 DOWNTO 0);
temp11 <= full_flag4 & half_flag4;

PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (RST = '1') THEN
vlcode_ac1 <= "000000000000000000"; codelength_ac1 <= "00000";
ELSE
IF (eob = '1' AND scan_type = '1') THEN
vlcode_ac1 <= "000000000000000010"; -- NOTE 2
codelength_ac1 <= "00010";   -- NOTE 2
ELSE
IF (eob = '1' AND scan_type = '0') THEN
vlcode_ac1 <= "000000000000000110";
codelength_ac1 <= "00100";   -- NOTE 2
ELSE
IF (cntr64 = "0000001" AND (rl_in(17 DOWNTO 12) &
rl_in(10 DOWNTO 0)) = "00000000000000001") THEN
vlcode_ac1 <= "00000000000000001" & rl_in(11);
codelength_ac1 <= "00010"; -- note3, DC coeff
ELSE
--******************* scan type = x, run = x, level = 1 *******
CASE temp10 IS
WHEN 'X' & "XXXXXX" &"00000000001"  =>   -- level = 1
CASE rl_in(17 DOWNTO 12) IS --run
WHEN "010001" => --17
vlcode_ac1 <= "00000000000011111" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "010010" => --18
vlcode_ac1 <= "00000000000011010" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "010011" => --19
vlcode_ac1 <= "00000000000011001" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "010100" => --20
vlcode_ac1 <= "00000000000010111" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "010101" => --21
vlcode_ac1 <= "00000000000010110" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "010110" => --22
vlcode_ac1 <= "00000000000011111" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "010111" => --23
vlcode_ac1 <= "00000000000011110" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "011000" => --24
vlcode_ac1 <="00000000000011101" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "011001" => --25
vlcode_ac1 <= "00000000000011100" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "011010" => --26
vlcode_ac1 <= "00000000000011011" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "011011" => --27
vlcode_ac1 <= "00000000000011111" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "011100" => --28
vlcode_ac1 <= "00000000000011110" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "011101" => --29
vlcode_ac1 <= "00000000000011101" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "011110" => --30
vlcode_ac1 <= "00000000000011100" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "011111" => --31
vlcode_ac1 <= "00000000000011011" & rl_in(11);
codelength_ac1 <= "10001";
WHEN OTHERS =>NULL;
END CASE;
WHEN 'X' & "XXXXXX" & "00000000010" => --level = 2
CASE rl_in(17 DOWNTO 12) IS --(run)
WHEN "000110" => --6
vlcode_ac1 <= "00000000000011110" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "000111" => --7
vlcode_ac1 <= "00000000000010101" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "001000" => --8
vlcode_ac1 <= "00000000000010001" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "001001" => --9
vlcode_ac1 <= "00000000000010001" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "001010" => --10
vlcode_ac1 <= "00000000000010000" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "001011" => --11
vlcode_ac1 <= "00000000000011010" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "001100" => --12
vlcode_ac1 <= "00000000000011001" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "001101" => --13
vlcode_ac1 <= "00000000000011000" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "001110" => --14
vlcode_ac1 <= "00000000000010111" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "001111" => --15
vlcode_ac1 <= "00000000000010110" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "010000" => --16
vlcode_ac1 <= "00000000000010101" & rl_in(11);
codelength_ac1 <= "10001";
WHEN OTHERS => NULL;
END CASE;
WHEN 'X' & "XXXXXX" & "00000000011" => --level = 3
CASE rl_in(17 DOWNTO 12) IS --(run)
WHEN "000011" => --3
vlcode_ac1 <= "00000000000011100" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "000100" => --4
vlcode_ac1 <= "00000000000010010" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "000101" => --5
vlcode_ac1 <= "00000000000010010" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "000110" => --6
vlcode_ac1 <= "00000000000010100" & rl_in(11);
codelength_ac1 <= "10001";
WHEN OTHERS => NULL;
END CASE;
WHEN 'X' & "000000" & "XXXXXXXXXXX" =>  --run = 0
CASE temp4 IS --(level)
WHEN "000000010000" => --16
vlcode_ac1 <= "00000000000011111" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000010001" => --17
vlcode_ac1 <= "00000000000011110" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000010010" => --18
vlcode_ac1 <= "00000000000011101" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000010011" => --19
vlcode_ac1 <= "00000000000011100" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000010100" => --20
vlcode_ac1 <= "00000000000011011" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000010101" => --21
vlcode_ac1 <= "00000000000011010" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000010110" => --22
vlcode_ac1 <= "00000000000011001" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000010111" => --23
vlcode_ac1 <= "00000000000011000" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000011000" => --24
vlcode_ac1 <= "00000000000010111" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000011001" => --25
vlcode_ac1 <= "00000000000010110" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000011010" => --26
vlcode_ac1 <= "00000000000010101" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000011011" => --27
vlcode_ac1 <= "00000000000010100" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000011100" => --28
vlcode_ac1 <= "00000000000010011" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000011101" => --29
vlcode_ac1 <= "00000000000010010" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000011110" => --30
vlcode_ac1 <= "00000000000010001" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000011111" => --31
vlcode_ac1 <= "00000000000010000" & rl_in(11);
codelength_ac1 <= "01111";
WHEN "000000100000" => --32
vlcode_ac1 <= "00000000000011000" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000100001" => --33
vlcode_ac1 <= "00000000000010111" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000100010" => --34
vlcode_ac1 <= "00000000000010110" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000100011" => --35
vlcode_ac1 <= "00000000000010101" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000100100" => --36
vlcode_ac1 <= "00000000000010100" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000100101" => --37
vlcode_ac1 <= "00000000000010011" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000100110" => --38
vlcode_ac1 <= "00000000000010010" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000100111" => --39
vlcode_ac1 <= "00000000000010001" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000101000" => --40
vlcode_ac1 <= "00000000000010000" & rl_in(11);
codelength_ac1 <= "10000";
WHEN OTHERS => NULL;
END CASE;
WHEN 'X' & "000001" &  "XXXXXXXXXXX" => -- run = 1
CASE temp5 IS --(level)
WHEN "000000000110" => --6
vlcode_ac1 <= "00000000000010110" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "000000000111" => --7
vlcode_ac1 <= "00000000000010101" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "000000001000" => --8
vlcode_ac1 <= "00000000000011111" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000001001" => --9
vlcode_ac1 <= "00000000000011110" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000001010" => --10
vlcode_ac1 <= "00000000000011101" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000001011" => --11
vlcode_ac1 <= "00000000000011100" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000001100" => --12
vlcode_ac1 <= "00000000000011011" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000001101" => --13
vlcode_ac1 <= "00000000000011010" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000001110" => --14
vlcode_ac1 <= "00000000000011001" & rl_in(11);
codelength_ac1 <= "10000";
WHEN "000000001111" => --15
vlcode_ac1 <= "00000000000010011" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "000000010000" => --16
vlcode_ac1 <= "00000000000010010" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "000000010001" => --17
vlcode_ac1 <= "00000000000010001" & rl_in(11);
codelength_ac1 <= "10001";
WHEN "000000010010" => --18
vlcode_ac1 <= "00000000000010000" & rl_in(11);
codelength_ac1 <= "10001";
WHEN OTHERS => NULL;
END CASE;
WHEN 'X' & "000010" & "00000000101" =>  -- scan type = x, run = 2, level = 5
vlcode_ac1 <= "00000000000010100" & rl_in(11);
codelength_ac1 <= "01110";
WHEN 'X' & "000011" & "00000000011" => -- scan type = x, run = 3, level = 4
vlcode_ac1 <= "00000000000010011" & rl_in(11);
codelength_ac1 <= "01110";
WHEN '0' & "XXXXXX" & "00000000001" =>  -- scan type = 0, run = x, level = 1
CASE rl_in(17 DOWNTO 12) IS --(run)
WHEN "000001" => --1
vlcode_ac1 <= "00000000000000011" & rl_in(11);
codelength_ac1 <= "00100";
WHEN "000010" => --2
vlcode_ac1 <= "00000000000000101" & rl_in(11);
codelength_ac1 <= "00101";
WHEN "000011" => --3
vlcode_ac1 <= "00000000000000111" & rl_in(11);
codelength_ac1 <= "00110";
WHEN "000100" =>  --4
vlcode_ac1 <= "00000000000000110" & rl_in(11);
codelength_ac1 <= "00110";
WHEN "000101" =>  --5
vlcode_ac1 <= "00000000000000111" & rl_in(11);
codelength_ac1 <= "00111";
WHEN "000110" => --6
vlcode_ac1 <= "00000000000000101" & rl_in(11);
codelength_ac1 <= "00111";
WHEN "000111" =>  --7
vlcode_ac1 <= "00000000000000100" & rl_in(11);
codelength_ac1 <= "00111";
WHEN "001000" =>  --8
vlcode_ac1 <= "00000000000000111" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "001001" => --9
vlcode_ac1 <= "00000000000000101" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "001010" => --10
vlcode_ac1 <= "00000000000100111" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "001011" => --11
vlcode_ac1 <= "00000000000100011" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "001100" => --12
vlcode_ac1 <= "00000000000100010" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "001101" =>  --13
vlcode_ac1 <= "00000000000100000" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "001110" => --14
vlcode_ac1 <= "00000000000001110" & rl_in(11);
codelength_ac1 <= "01011";
WHEN "001111" => --15
vlcode_ac1 <= "00000000000001101" & rl_in(11);
codelength_ac1 <= "01011";
WHEN "010000" => --16
vlcode_ac1 <= "00000000000001000" & rl_in(11);
codelength_ac1 <= "01011";
WHEN OTHERS =>  NULL;
END CASE;
WHEN '1' & "XXXXXX" & "00000000001" => -- scan type = 1, run = x, level = 1
CASE rl_in(17 DOWNTO 12) IS --(run)
WHEN "000001" => --1
vlcode_ac1 <= "00000000000000010" & rl_in(11);
codelength_ac1 <= "00100";
WHEN "000010" => --2
vlcode_ac1 <= "00000000000000101" & rl_in(11);
codelength_ac1 <= "00110";
WHEN "000011" =>  --3
vlcode_ac1 <= "00000000000000111" & rl_in(11);
codelength_ac1 <= "00110";
WHEN "000100" =>  --4
vlcode_ac1 <= "00000000000000110" & rl_in(11);
codelength_ac1 <= "00111";
WHEN "000101" =>  --5
vlcode_ac1 <= "00000000000000111" & rl_in(11);
codelength_ac1 <= "00111";
WHEN "000110" => --6
vlcode_ac1 <= "00000000000000110" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "000111" => --7
vlcode_ac1 <= "00000000000000100" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "001000" => --8
vlcode_ac1 <= "00000000000000101" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "001001" => --9
vlcode_ac1 <= "00000000001111000" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "001010" => --10
vlcode_ac1 <= "00000000001111010" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "001011" => --11
vlcode_ac1 <= "00000000000100001" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "001100" => --12
vlcode_ac1 <= "00000000000100101" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "001101" => --13
vlcode_ac1 <= "00000000000100100" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "001110" => --14
vlcode_ac1 <= "00000000000000101" & rl_in(11);
codelength_ac1 <= "01010";
WHEN "001111" => --15
vlcode_ac1 <= "00000000000000111" & rl_in(11);
codelength_ac1 <= "01010";
WHEN "010000" => --16
vlcode_ac1 <= "00000000000001101" & rl_in(11);
codelength_ac1 <= "01011";
WHEN OTHERS => NULL;
END CASE;
WHEN '0' & "000000" & "XXXXXXXXXXX" => -- scan type = 0, run = 0, level = x
CASE temp6 IS --(level)
WHEN "000000000010" => --2
vlcode_ac1 <= "00000000000000100" & rl_in(11);
codelength_ac1 <= "00101";
WHEN "000000000011" => --3
vlcode_ac1 <= "00000000000000101" & rl_in(11);
codelength_ac1 <= "00110";
WHEN "000000000100" => --4
vlcode_ac1 <= "00000000000000110" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "000000000101" => --5
vlcode_ac1 <= "00000000000100110" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "000000000110" => --6
vlcode_ac1 <= "00000000000100001" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "000000000111" => --7
vlcode_ac1 <= "00000000000001010" & rl_in(11);
codelength_ac1 <= "01011";
WHEN "000000001000" => --8
vlcode_ac1 <= "00000000000011101" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "000000001001" => --9
vlcode_ac1 <= "00000000000011000" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "000000001010" => --10
vlcode_ac1 <= "00000000000010011" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "000000001011" => --11
vlcode_ac1 <= "00000000000010000" & rl_in(11);
codelength_ac1 <= "01101";
WHEN "000000001100" => --12
vlcode_ac1 <= "00000000000011010" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "000000001101" =>  --13
vlcode_ac1 <= "00000000000011001" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "000000001110" => --14
vlcode_ac1 <= "00000000000011000" & rl_in(11);
codelength_ac1 <= "01110";
WHEN "000000001111" => --15
vlcode_ac1 <= "00000000000010111" & rl_in(11);
codelength_ac1 <= "01110";
WHEN OTHERS => NULL;
END CASE;
WHEN '1' & "000000" & "XXXXXXXXXXX" => -- scan type = 1, run = 0, level = x
CASE temp7 IS --(level)
WHEN "000000000001" => --1
vlcode_ac1 <= "00000000000000010" & rl_in(11);
codelength_ac1 <= "00011";
WHEN "000000000010" => --2
vlcode_ac1 <= "00000000000000110" & rl_in(11);
codelength_ac1 <= "00100";
WHEN "000000000011" => --3
vlcode_ac1 <= "00000000000000111" & rl_in(11);
codelength_ac1 <= "00101";
WHEN "000000000100" => --4
vlcode_ac1 <= "00000000000011100" & rl_in(11);
codelength_ac1 <= "00110";
WHEN "000000000101" => --5
vlcode_ac1 <= "00000000000011101" & rl_in(11);
codelength_ac1 <= "00110";
WHEN "000000000110" => --6
vlcode_ac1 <= "00000000000000101" & rl_in(11);
codelength_ac1 <= "00111";
WHEN "000000000111" => --7
vlcode_ac1 <= "00000000000000100" & rl_in(11);
codelength_ac1 <= "00111";
WHEN "000000001000" => --8
vlcode_ac1 <= "00000000001111011" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "000000001001" => --9
vlcode_ac1 <= "00000000001111100" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "000000001010" => --10
vlcode_ac1 <= "00000000000100011" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "000000001011" => --11
vlcode_ac1 <= "00000000000100010" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "000000001100" => --12
vlcode_ac1 <= "00000000011111010" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "000000001101" => --13
vlcode_ac1 <= "00000000011111011" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "000000001110" => --14
vlcode_ac1 <= "00000000011111110" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "000000001111" => --15
vlcode_ac1 <= "00000000011111111" & rl_in(11);
codelength_ac1 <= "01001";
WHEN OTHERS =>  NULL;
END CASE;
WHEN '0' & "XXXXXX" & "00000000010" => -- scan type = 0, run = x, level = 2
CASE temp8 IS --(level)
WHEN "000000000001" => --1
vlcode_ac1 <=  "00000000000000110" & rl_in(11) ;
codelength_ac1 <= "00111";
WHEN "000000000010" => --2
vlcode_ac1 <= "00000000000000100" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "000000000011" => --3
vlcode_ac1 <= "00000000000100100" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "000000000100" => --4
vlcode_ac1 <= "00000000000001111" & rl_in(11);
codelength_ac1 <= "01011";
WHEN "000000000101" =>  --5
vlcode_ac1 <= "00000000000001001" & rl_in(11);
codelength_ac1 <= "01011";
WHEN OTHERS => NULL;
END CASE;
WHEN '1' & "XXXXXX" & "00000000010" =>  -- scan type = 1, run = x, level = 2
CASE temp9 IS --(level)
WHEN "000000000001" => --1
vlcode_ac1 <= "00000000000000110" & rl_in(11);
codelength_ac1 <= "00110";
WHEN "000000000010" => --2
vlcode_ac1 <= "00000000000001110" & rl_in(11);
codelength_ac1 <= "01000";
WHEN "000000000011" => --3
vlcode_ac1 <= "00000000000100110" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "000000000100" => --4
vlcode_ac1 <= "00000000011111101" & rl_in(11);
codelength_ac1 <= "01001";
WHEN "000000000101" => --5
vlcode_ac1 <= "00000000000000100" & rl_in(11);
codelength_ac1 <= "01010";
WHEN OTHERS => NULL;
END CASE;
WHEN 'X' & "000010" & "00000000101" => -- scan_type = 0, EOB
vlcode_ac1 <= "00000000000010100" & rl_in(11);
codelength_ac1 <= "01110";
WHEN 'X' & "000010" & "00000000101" => -- scan type = x, run = 2, level = 5
vlcode_ac1 <= "00000000000010100" & rl_in(11);
codelength_ac1 <= "01110";
WHEN 'X' & "000010" & "00000000101" => -- scan type = x, run = 2, level = 5
vlcode_ac1 <= "00000000000010100" & rl_in(11);
codelength_ac1 <= "01110";
WHEN 'X' & "000010" & "00000000101" => -- scan type = x, run = 2, level = 5
vlcode_ac1 <= "00000000000010100" & rl_in(11);
codelength_ac1 <= "01110";
WHEN 'X' & "000010" & "00000000101" => -- scan type = x, run = 2, level = 5
vlcode_ac1 <= "00000000000010100" & rl_in(11);
codelength_ac1 <= "01110";
WHEN 'X' & "000010" & "00000000101" => -- scan type = x, run = 2, level = 5
vlcode_ac1 <= "00000000000010100" & rl_in(11);
codelength_ac1 <= "01110";
WHEN OTHERS =>
vlcode_ac1 <= rl_in;
codelength_ac1 <= "10010";
END CASE;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;

--***************************************************************************
-- pipeline vlcode_ac1 and codelength_ac1 to match the 2 pipe stages of the
--  pipeline vlcode_ac1 and codelength_ac1 to match the 2 pipe stages of the
-- corresponding DC values

PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (RST = '1') THEN
vlcode_ac <= "000000000000000000";
codelength_ac <= "00000";
ELSE
vlcode_ac <= vlcode_ac1;
codelength_ac <= codelength_ac1;
END IF;
END IF;
END PROCESS;

--***************************************************************************
-- select code and codelength. Counter value set at 2 because of the 2 pipestages
--  select code and codelength. Counter value set at 2 because of the 2 pipestages
-- od the AC and DC codelengths and vl codes

PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
codelength1 <= "00000";
vlcode1 <= "000000000000000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1' AND cntr64 = "0000010") THEN
codelength1 <= '0' & codelength_dc;
vlcode1 <= "00000000" & vlcode_dc;
ELSE
codelength1 <= codelength_ac;
vlcode1 <= vlcode_ac;
END IF;
END IF;
END PROCESS;

--***************************************************************************
-- pipeline code and codelength. This is done to match the pipestages with
--  pipeline code and codelength. This is done to match the pipestages with
-- cl_sum_prev which is multiplied with vlcode.

PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
codelength2 <= "00000";
vlcode2 <= "000000000000000000";
vlcode3 <= "000000000000000000";
vlcode4 <= "000000000000000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
codelength2 <= codelength1;
vlcode2 <= vlcode1;
vlcode3 <= vlcode2;
vlcode4 <= vlcode3;
END IF;
END IF;
END PROCESS;

--***************************************************************************
-- The maximum length of the vlc code can be 18 bits + 6 bits = 24 bits. This happens
--  The maximum length of the vlc code can be 18 bits + 6 bits = 24 bits. This happens
-- when a run level pair not defined in the table is encountered. In this case , a 6 bit
-- escape code followed by 6 bit run code and 12 bit level code is used.  The minimum
-- length of the vlc code is 2 bits. This happens when encoding an "EOB" symbol. After
-- finding the vlc code for a particular run/level pair, the code is shifted into a
-- barrel shifter.
-- Every time there are 16 bits in the barrel shifter, the contends of the shifter is
-- enabled out as the huffman_out signal. Each run length value is read in and the corresponding
-- vlc code is found out (vlcode_dc or vlcode_ac1). For each code, the codelength is also
-- stored in a ROM. The codelengths are added up (cl_sum) and when it reaches 16 or 32,
-- the code is sent out.
-- The maximum  value for cl_sum happens when a 15 bit code is followed by a 24 bit
-- code. So the max. value for cl_sum is 15 + 24 = 39. The barrel shifter has 39 valid
-- registers. For ease of coding, 48 (3 * 16) registers are used. These registers are
-- divided into upper_reg, middle_reg and lower_reg. Each time upper_reg if full (ie.,
-- 16 or more bits in barrel shifter), the contends are sent out. The remaining bits
-- , if any, in the middle_reg are moved up to the upper_reg. If the barrel shifter
-- has 32 or more valid data, the upper and middle registers are full and the upper
-- reg data is sent out followed by the middle reg data. The remaining bits, if any
-- in the lower register is moved up to the upper register.

--***************************************************************************
-- calculate sum of codelength. set half flag and full flag . Half flags indicates
--  calculate sum of codelength. set half flag and full flag . Half flags indicates
-- that the upper_reg is full and full flag indicates that the lower register is full.
-- cl_sum_prev gives the sum of the codelengths which is used to set the flags. cl_sum
-- is used to find out the number of shifts to be done in the barrel shifts.

PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
cl_sum <= "100111";
cl_sum_prev <= "000000";
half_flag1 <= '0';
full_flag1 <= '0';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (cl_sum_rdy = '1') THEN
IF (cl_sum_prev < "010000") THEN
cl_sum_prev <= "0" & codelength1 + cl_sum_prev;
cl_sum <= "100111" - cl_sum_prev;
half_flag1 <= '0';
full_flag1 <= '0';
ELSE
IF (cl_sum_prev<="100000" AND cl_sum_prev >= "010000")
THEN
cl_sum_prev <= "0" & codelength1 + (cl_sum_prev -
"010000");
cl_sum <= "100111" - cl_sum_prev;
half_flag1 <= '1';
full_flag1 <= '0';
ELSE
IF (cl_sum_prev >= "100000") THEN
cl_sum_prev <= "0" & codelength1 + (cl_sum_prev -
"100000");
cl_sum <= "100111" - cl_sum_prev;
half_flag1 <= '1';
full_flag1 <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;

--***************************************************************************
-- barrel shifting done using multiplier. Barrel shifting coefficients are
--  barrel shifting done using multiplier. Barrel shifting coefficients are
-- stored in a ROM and selected depending on the value of cl_sum

PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (RST = '1') THEN
cl_sum_shift <= "000000000000000000000000000000000000000";
ELSE
CASE cl_sum IS
WHEN "000000" =>
cl_sum_shift <= "000000000000000000000000000000000000000";
WHEN "000001" =>
cl_sum_shift <= "000000000000000000000000000000000000010";
WHEN "000010" =>
cl_sum_shift <= "000000000000000000000000000000000000100";
WHEN "000011" =>
cl_sum_shift <= "000000000000000000000000000000000001000";
WHEN "000100" =>
cl_sum_shift <= "000000000000000000000000000000000010000";
WHEN "000101" =>
cl_sum_shift <= "000000000000000000000000000000000100000";
WHEN "000110" =>
cl_sum_shift <= "000000000000000000000000000000001000000";
WHEN "000111" =>
cl_sum_shift <= "000000000000000000000000000000010000000";
WHEN "001000" =>
cl_sum_shift <= "000000000000000000000000000000100000000";
WHEN "001001" =>
cl_sum_shift <= "000000000000000000000000000001000000000";
WHEN "001010" =>
cl_sum_shift <= "000000000000000000000000000010000000000";
WHEN "001011" =>
cl_sum_shift <= "000000000000000000000000000100000000000";
WHEN "001100" =>
cl_sum_shift <= "000000000000000000000000001000000000000";
WHEN "001101" =>
cl_sum_shift <= "000000000000000000000000010000000000000";
WHEN "001110" =>
cl_sum_shift <= "000000000000000000000000100000000000000";
WHEN "001111" =>
cl_sum_shift <= "000000000000000000000001000000000000000";
WHEN "010000" =>
cl_sum_shift <= "000000000000000000000010000000000000000";
WHEN "010001" =>
cl_sum_shift <= "000000000000000000000100000000000000000";
WHEN "010010" =>
cl_sum_shift <= "000000000000000000001000000000000000000";
WHEN "010011" =>
cl_sum_shift <= "000000000000000000010000000000000000000";
WHEN "010100" =>
cl_sum_shift <= "000000000000000000100000000000000000000";
WHEN "010101" =>
cl_sum_shift <= "000000000000000001000000000000000000000";
WHEN "010110" =>
cl_sum_shift <= "000000000000000010000000000000000000000";
WHEN "010111" =>
cl_sum_shift <= "000000000000000100000000000000000000000";
WHEN "011000" =>
cl_sum_shift <= "000000000000001000000000000000000000000";
WHEN "011001" =>
cl_sum_shift <= "000000000000010000000000000000000000000";
WHEN "011010" =>
cl_sum_shift <= "000000000000100000000000000000000000000";
WHEN "011011" =>
cl_sum_shift <= "000000000001000000000000000000000000000";
WHEN "011100" =>
cl_sum_shift <= "000000000010000000000000000000000000000";
WHEN "011101" =>
cl_sum_shift <= "000000000100000000000000000000000000000";
WHEN "011110" =>
cl_sum_shift <= "000000001000000000000000000000000000000";
WHEN "011111" =>
cl_sum_shift <= "000000010000000000000000000000000000000";
WHEN "100000" =>
cl_sum_shift <= "000000100000000000000000000000000000000";
WHEN "100001" =>
cl_sum_shift <= "000001000000000000000000000000000000000";
WHEN "100010" =>
cl_sum_shift <= "000010000000000000000000000000000000000";
WHEN "100011" =>
cl_sum_shift <= "000100000000000000000000000000000000000";
WHEN "100100" =>
cl_sum_shift <= "001000000000000000000000000000000000000";
WHEN "100101" =>
cl_sum_shift <= "010000000000000000000000000000000000000";
WHEN "100110" =>
cl_sum_shift <= "100000000000000000000000000000000000000";
WHEN OTHERS  =>
cl_sum_shift <= "000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;

--***************************************************************************
-- multiplier used to do barrel shifting of codeword. flags pipeleined to match
--  multiplier used to do barrel shifting of codeword. flags pipeleined to match
-- the pipe line stages of upper, middle and lower registers.

PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
mult_out_int <= (OTHERS => '0');
full_flag2 <= '0';
half_flag2 <= '0';
full_flag3 <= '0';
half_flag3 <= '0';
full_flag4 <= '0';
half_flag4 <= '0';
full_flag5 <= '0';
half_flag5 <= '0';
full_flag6 <= '0';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
mult_out_int <=  vlcode4 * cl_sum_shift;
full_flag2 <= full_flag1;
half_flag2 <= half_flag1;
full_flag3 <= full_flag2;
half_flag3 <= half_flag2;
full_flag4 <= full_flag3;
half_flag4 <= half_flag3;
full_flag5 <= full_flag4;
half_flag5 <= half_flag4;
full_flag6 <= full_flag5;
END IF;
END IF;
END PROCESS;

mult_out <= mult_out_int (38 downto 0);
--***************************************************************************
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
upper_reg1 <= "0000000000000000";
middle_reg1 <= "0000000000000000";
lower_reg1 <= "0000000000000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
CASE temp11 IS
WHEN "00" =>
upper_reg1(16 DOWNTO 1) <= mult_out(38 DOWNTO 23)
OR upper_reg1(16 DOWNTO 1);
middle_reg1 <= mult_out(22 DOWNTO 7);
lower_reg1 <= mult_out(6 DOWNTO 0) &
"000000000";
WHEN "01" =>
upper_reg1(16 DOWNTO 1) <= mult_out(38 DOWNTO 23)
OR middle_reg1(16 DOWNTO 1);
middle_reg1 <= mult_out(22 DOWNTO 7);
lower_reg1 <= mult_out(6 DOWNTO 0) &
"000000000";
WHEN "11" =>
upper_reg1 <= mult_out(38 DOWNTO 23) OR
lower_reg1;
middle_reg1 <= mult_out(22 DOWNTO 7);
lower_reg1 <= "0000000000000000";
WHEN OTHERS  =>
upper_reg1 <= upper_reg1;
middle_reg1 <= middle_reg1;
lower_reg1 <= lower_reg1;

END CASE;
END IF;
END IF;
END PROCESS;

--***************************************************************************
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
upper_reg2 <= "0000000000000000";
middle_reg2 <= "0000000000000000";
middle_reg3 <= "0000000000000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
upper_reg2 <= upper_reg1;
middle_reg2 <= middle_reg1;
middle_reg3 <= middle_reg2;
END IF;
END IF;
END PROCESS;

--***************************************************************************
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
huffman_out <= "0000000000000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
IF (half_flag5 = '1') THEN
huffman_out <= upper_reg2;
ELSE
IF (full_flag6 = '1') THEN
huffman_out <= middle_reg3;
END IF;
END IF;
END IF;
END IF;
END PROCESS;

--***************************************************************************
-- counter that counts upto 64.
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
cntr64 <= "1000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
IF (cntr64 < "1000000") THEN
cntr64 <= cntr64 + "0000001";
ELSE
cntr64 <= "0000001";
END IF;
END IF;
END IF;
END PROCESS;

-- cl_sum starts after 2 clks from reset.
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
cl_sum_rdy <= '0';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (cntr64 = "0000010") THEN
cl_sum_rdy <= '1';
ELSE
cl_sum_rdy <= cl_sum_rdy;
END IF;
END IF;
END PROCESS;

--***************************************************************************
-- counter that counts upto 64.
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
rdy_out <= '0';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
rdy_out <= '1';
END IF;
END IF;
END PROCESS;
--***************************************************************************

END translated;

]]> http://blog.ektel.com.np/2012/04/huffman-encoder-vhdl-code/feed/ 0 Huffman Encoder Verilog HDL code http://blog.ektel.com.np/2012/04/huffman-encoder-verilog-hdl-code/?utm_source=rss&utm_medium=rss&utm_campaign=huffman-encoder-verilog-hdl-code http://blog.ektel.com.np/2012/04/huffman-encoder-verilog-hdl-code/#comments Fri, 20 Apr 2012 01:42:34 +0000 admin http://blog.ektel.com.np/?p=341 /**********************************************************************/
//scale factor --- how many bits ?
`timescale 1ns/1ps

module huffman_en   (CLK, RST, rdy_in, rl_in, dc_in, scan_type, luma,
huffman_out, eob, rdy_out);

output [15:0] huffman_out;
output rdy_out;
input CLK, RST, eob;
input [11:0] dc_in;
input rdy_in,  luma;
input scan_type;           /* used to choose b/n intra(0) & non-intra(1)
blocks */
input[17:0] rl_in;   /* run[5:0] + value[11:0] */
/* signals */

reg[6:0] cntr64;
reg  rdy_out,cl_sum_rdy;
reg[3:0] size/* synthesis syn_romstyle = "select_rom" */;
reg[5:0] cl_sum, cl_sum_prev;
reg[15:0] huffman_out;
reg[3:0] codelength_dc  /* synthesis syn_romstyle = "block_rom" */;
reg[4:0] codelength_ac,codelength1,codelength2;
reg[4:0] codelength_ac1;
reg[9:0] vlcode_dc  /* synthesis syn_romstyle = "block_rom" */;
reg[17:0] vlcode1, vlcode2,vlcode3,vlcode4;
reg[17:0] vlcode_ac1,vlcode_ac;
reg[38:0] cl_sum_shift;
reg full_flag1,half_flag1,half_flag2,full_flag2,half_flag3,full_flag3;
reg full_flag4,half_flag4,full_flag5,full_flag6,half_flag5;
reg[38:0] mult_out;
reg[16:1] upper_reg1,middle_reg1,lower_reg1;
reg[16:1] upper_reg2, middle_reg2, middle_reg3;
/*****************************************************************************/

/* Find the size for the "Differential_DC" value. The differential_dc_size gives the number of
bits to be used to denote the DC_difference value. ram_dc_diff . Table 1 in document*/

always @ (posedge CLK)
begin
casex (dc_in)
12'b111111111111 :  size = 4'd1;
12'b11111111110x :   size = 4'd2;
12'b1111111110xx :   size = 4'd3;
12'b111111110xxx :   size = 4'd4;
12'b11111110xxxx :   size = 4'd5;
12'b1111110xxxxx :   size = 4'd6;
12'b111110xxxxxx :   size = 4'd7;
12'b11110xxxxxxx :   size = 4'd8;
12'b1110xxxxxxxx :   size = 4'd9;
12'b110xxxxxxxxx :   size = 4'd10;
12'b10xxxxxxxxxx :   size = 4'd11;
12'b000000000000 :   size = 4'd0;
12'b000000000001 :   size = 4'd1;
12'b00000000001x :   size = 4'd2;
12'b0000000001xx :   size = 4'd3;
12'b000000001xxx :   size = 4'd4;
12'b00000001xxxx :   size = 4'd5;
12'b0000001xxxxx :   size = 4'd6;
12'b000001xxxxxx :   size = 4'd7;
12'b00001xxxxxxx :   size = 4'd8;
12'b0001xxxxxxxx :   size = 4'd9;
12'b001xxxxxxxxx :   size = 4'd10;
12'b01xxxxxxxxxx :  size = 4'd11;
default: size = 4'd0;
endcase
end

/*****************************************************************************/
/* variable length code and the corresponding code length for DC_Differential */
/* After finding the size of the DC_Differential, the variable length code used to denote it is found.
For example, if the size is 10, 10 bits are used to denote the dc_differential value and a variable
length code prefix of "111111110" is used along with the 10 bit value. */

/* luma = 1'b1 denotes a luminance block and lume = 1'b0 denotes a chrominance block */

always @ (posedge CLK)
begin
if (RST)
begin
vlcode_dc <= 10'b0; codelength_dc <= 4'd0;
end
else if (cntr64 == 1'b1)
begin
case (luma)
1'b1: begin
case (size) //ram_dc_size1
4'd0 : begin vlcode_dc <= 10'b0000000100; codelength_dc <= 4'd3; end
4'd1 : begin vlcode_dc <= 10'b0000000000; codelength_dc <= 4'd2; end
4'd2 : begin vlcode_dc <= 10'b0000000001; codelength_dc <= 4'd2; end
4'd3 : begin vlcode_dc <= 10'b0000000101; codelength_dc <= 4'd3; end
4'd4 : begin vlcode_dc <= 10'b0000000110; codelength_dc <= 4'd3; end
4'd5 : begin vlcode_dc <= 10'b0000001110; codelength_dc <= 4'd4; end
4'd6 : begin vlcode_dc <= 10'b0000011110; codelength_dc <= 4'd5; end
4'd7 : begin vlcode_dc <= 10'b0000111110; codelength_dc <= 4'd6; end
4'd8 : begin vlcode_dc <= 10'b0001111110; codelength_dc <= 4'd7; end
4'd9 : begin vlcode_dc <= 10'b0011111110; codelength_dc <= 4'd8; end
4'd10 : begin vlcode_dc <= 10'b0111111110; codelength_dc <= 4'd9; end
4'd11 : begin vlcode_dc <= 10'b0111111111; codelength_dc <= 4'd9; end
default: begin vlcode_dc <= 10'b0; codelength_dc <= 4'd0; end
endcase
end
//always @(size)
1'b0: begin
case (size) //ram_dc_size2
4'd0 : begin vlcode_dc <= 10'b0000000000; codelength_dc <= 4'd2; end
4'd1 : begin vlcode_dc <= 10'b0000000001; codelength_dc <= 4'd2; end
4'd2 : begin vlcode_dc <= 10'b0000000010; codelength_dc <= 4'd2; end
4'd3 : begin vlcode_dc <= 10'b0000000110; codelength_dc <= 4'd3; end
4'd4 : begin vlcode_dc <= 10'b0000001110; codelength_dc <= 4'd4; end
4'd5 : begin vlcode_dc <= 10'b0000011110; codelength_dc <= 4'd5; end
4'd6 : begin vlcode_dc <= 10'b0000111110; codelength_dc <= 4'd6; end
4'd7 : begin vlcode_dc <= 10'b0001111110; codelength_dc <= 4'd7; end
4'd8 : begin vlcode_dc <= 10'b0011111110; codelength_dc <= 4'd8; end
4'd9 : begin vlcode_dc <= 10'b0111111110; codelength_dc <= 4'd9; end
4'd10 : begin vlcode_dc <= 10'b1111111110; codelength_dc <= 4'd10; end
4'd11 : begin vlcode_dc <= 10'b1111111111; codelength_dc <= 4'd10; end
default: begin vlcode_dc <= 10'b0; codelength_dc <= 4'd0; end

endcase
end
endcase
end
end

/*****************************************************************************/
/* variable length code and corresponding code length for AC coefficients.
Table zero is used for intra blocks anf table one is used for non-intra
blocks.  For a run/level pair not defined in table zero or one, an escape
code followed by a 6 bit run symbol and 12 bit level is used.*/
//assign run_level_pair <= {run_in,level_in};

/*always @ (posedge CLK)
begin
if (RST)
begin vlcode_ac1 <= {18'b0}; codelength_ac1 <= 5'd0; end
else
begin if (rdy_in == 1'b1)
begin
case(rl_in)
18'b000000000000000001:
begin  vlcode_ac1 <= {17'b00000000000001010,rl_in[11]}; codelength_ac1 <= 5'd5; end
18'b000000000000000101:
begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd4; end
18'b000000000000001010:
begin  vlcode_ac1 <= {17'b00000000000001110,rl_in[11]}; codelength_ac1 <= 5'd5; end
18'b000001000000000101:
begin  vlcode_ac1 <= {18'b111100001111001101}; codelength_ac1 <= 5'd18; end
18'b000011000000000111:
begin  vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd6; end
18'b000111000000001001:
begin  vlcode_ac1 <= {17'b00000000000000000,rl_in[11]}; codelength_ac1 <= 5'd5; end
18'b010000000000010000:
begin  vlcode_ac1 <= {17'b10000000000010110,rl_in[11]}; codelength_ac1 <= 5'd7; end
18'b010101000000001001:
begin  vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd7; end
default:
begin  vlcode_ac1 <= {18'b111111111111111111}; codelength_ac1 <= 5'd18; end
endcase
end
end
end*/

/*****************************************************************************/

always @ (posedge CLK)
if (RST)
begin vlcode_ac1 <= {18'b0}; codelength_ac1 <= 5'd0; end
else
begin
if (eob == 1'b1 && scan_type == 1'b1)
begin  vlcode_ac1 <= 000000000000000010; codelength_ac1 <= 5'd2; end // NOTE 2
else if (eob == 1'b1 && scan_type == 1'b0)
begin  vlcode_ac1 <= 000000000000000110; codelength_ac1 <= 5'd4; end // NOTE 2
else if (cntr64 == 7'b0000001 && ({rl_in[17:12],rl_in[10:0]}) == 17'b00000000000000001)
begin vlcode_ac1 <= {17'b00000000000000001,rl_in[11]};
codelength_ac1 <= 5'd2; end // note3, DC coeff
else
begin

/******************** scan type = x, run = x, level = 1 ********/

casex ({scan_type,rl_in[17:12],rl_in[10:0]})//(check)

{1'bx,6'bx,11'b00000000001}: // level = 1
begin
case({rl_in[17:12]}) //run
6'b010001: //17
begin  vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b010010: //18
begin  vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b010011: //19
begin  vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b010100: //20
begin  vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b010101: //21
begin  vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b010110: //22
begin  vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b010111: //23
begin  vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b011000: //24
begin  vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b011001: //25
begin  vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b011010: //26
begin  vlcode_ac1 <= {17'b00000000000011011,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b011011: //27
begin  vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b011100: //28
begin  vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b011101: //29
begin  vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b011110: //30
begin  vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b011111: //31
begin  vlcode_ac1 <= {17'b00000000000011011,rl_in[11]}; codelength_ac1 <= 5'd17; end
endcase
end
/******************** scan type = x, run = x, level = 2 ********/
{1'bx,6'bx,11'b00000000010}: //level = 2
begin
case({rl_in[17:12]}) //(run)
6'b000110: //6
begin  vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b000111: //7
begin  vlcode_ac1 <= {17'b00000000000010101,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b001000: //8
begin  vlcode_ac1 <= {17'b00000000000010001,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b001001: //9
begin  vlcode_ac1 <= {17'b00000000000010001,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b001010: //10
begin  vlcode_ac1 <= {17'b00000000000010000,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b001011: //11
begin  vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b001100: //12
begin  vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b001101: //13
begin  vlcode_ac1 <= {17'b00000000000011000,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b001110: //14
begin  vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b001111: //15
begin  vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b010000: //16
begin  vlcode_ac1 <= {17'b00000000000010101,rl_in[11]}; codelength_ac1 <= 5'd17; end
endcase
end
/******************** scan type = x, run = x, level = 3 ********/
{1'bx,6'bx,11'b00000000011}: //level = 3
begin
case ({rl_in[17:12]}) //(run)
6'b000011: //3
begin  vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b000100: //4
begin  vlcode_ac1 <= {17'b00000000000010010,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b000101: //5
begin  vlcode_ac1 <= {17'b00000000000010010,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b000110: //6
begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd17; end
endcase
end
/******************** scan type = x, run = 0, level = x ********/
{1'bx,6'b000000,11'bx}: //run = 0
begin
case ({1'b0,rl_in[10:0]}) //(level)
12'b000000010000: //16
begin  vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010001: //17
begin  vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010010: //18
begin  vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010011: //19
begin  vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010100: //20
begin  vlcode_ac1 <= {17'b00000000000011011,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010101: //21
begin  vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010110: //22
begin  vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010111: //23
begin  vlcode_ac1 <= {17'b00000000000011000,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011000: //24
begin  vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011001: //25
begin  vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011010: //26
begin  vlcode_ac1 <= {17'b00000000000010101,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011011: //27
begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011100: //28
begin  vlcode_ac1 <= {17'b00000000000010011,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011101: //29
begin  vlcode_ac1 <= {17'b00000000000010010,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011110: //30
begin  vlcode_ac1 <= {17'b00000000000010001,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011111: //31
begin  vlcode_ac1 <= {17'b00000000000010000,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000100000: //32
begin  vlcode_ac1 <= {17'b00000000000011000,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000100001: //33
begin  vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000100010: //34
begin  vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000100011: //35
begin  vlcode_ac1 <= {17'b00000000000010101,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000100100: //36
begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000100101: //37
begin  vlcode_ac1 <= {17'b00000000000010011,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000100110: //38
begin  vlcode_ac1 <= {17'b00000000000010010,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000100111: //39
begin  vlcode_ac1 <= {17'b00000000000010001,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000101000: //40
begin  vlcode_ac1 <= {17'b00000000000010000,rl_in[11]}; codelength_ac1 <= 5'd16; end
endcase
end
/******************** scan type = x, run = 1, level = x ********/
{1'bx,6'b000001,11'bx}: // run = 1
begin
case ({1'b0,rl_in[10:0]}) //(level)
12'b000000000110: //6
begin  vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd14; end
12'b000000000111: //7
begin  vlcode_ac1 <= {17'b00000000000010101,rl_in[11]}; codelength_ac1 <= 5'd14; end
12'b000000001000: //8
begin  vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000001001: //9
begin  vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000001010: //10
begin  vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000001011: //11
begin  vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000001100: //12
begin  vlcode_ac1 <= {17'b00000000000011011,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000001101: //13
begin  vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000001110: //14
begin  vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd16; end
12'b000000001111: //15
begin  vlcode_ac1 <= {17'b00000000000010011,rl_in[11]}; codelength_ac1 <= 5'd17; end
12'b000000010000: //16
begin  vlcode_ac1 <= {17'b00000000000010010,rl_in[11]}; codelength_ac1 <= 5'd17; end
12'b000000010001: //17
begin  vlcode_ac1 <= {17'b00000000000010001,rl_in[11]}; codelength_ac1 <= 5'd17; end
12'b000000010010: //18
begin  vlcode_ac1 <= {17'b00000000000010000,rl_in[11]}; codelength_ac1 <= 5'd17; end
endcase
end

/***************************************************************************************/

{1'bx,6'b000010,11'b00000000101}: // scan type = x, run = 2, level = 5
begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd14; end
{1'bx,6'b000011,11'b00000000011}: // scan type = x, run = 3, level = 4
begin  vlcode_ac1 <= {17'b00000000000010011,rl_in[11]}; codelength_ac1 <= 5'd14; end

/***************************************************************************************/

{1'b0,6'bx,11'b00000000001}: // scan type = 0, run = x, level = 1
begin
case ({rl_in[17:12]}) //(run)
6'b000001 : //1
begin  vlcode_ac1 <= {17'b00000000000000011,rl_in[11]}; codelength_ac1 <= 5'd4; end
6'b000010 : //2
begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd5; end
6'b000011 : //3
begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd6; end
6'b000100 : //4
begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd6; end
6'b000101 : //5
begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd7; end
6'b000110 : //6
begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd7; end
6'b000111 : //7
begin  vlcode_ac1 <= {17'b00000000000000100,rl_in[11]}; codelength_ac1 <= 5'd7; end
6'b001000 : //8
begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd8; end
6'b001001 : //9
begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd8; end
6'b001010 : //10
begin  vlcode_ac1 <= {17'b00000000000100111,rl_in[11]}; codelength_ac1 <= 5'd9; end
6'b001011 : //11
begin  vlcode_ac1 <= {17'b00000000000100011,rl_in[11]}; codelength_ac1 <= 5'd9; end
6'b001100 : //12
begin  vlcode_ac1 <= {17'b00000000000100010,rl_in[11]}; codelength_ac1 <= 5'd9; end
6'b001101 : //13
begin  vlcode_ac1 <= {17'b00000000000100000,rl_in[11]}; codelength_ac1 <= 5'd9; end
6'b001110 : //14
begin  vlcode_ac1 <= {17'b00000000000001110,rl_in[11]}; codelength_ac1 <= 5'd11; end
6'b001111 : //15
begin  vlcode_ac1 <= {17'b00000000000001101,rl_in[11]}; codelength_ac1 <= 5'd11; end
6'b010000 : //16
begin  vlcode_ac1 <= {17'b00000000000001000,rl_in[11]}; codelength_ac1 <= 5'd11; end
endcase
end

/***************************************************************************************/

{1'b1,6'bx,11'b00000000001}: // scan type = 1, run = x, level = 1
begin
case ({rl_in[17:12]}) //(run)
6'b000001 : //1
begin  vlcode_ac1 <= {17'b00000000000000010,rl_in[11]}; codelength_ac1 <= 5'd4; end
6'b000010 : //2
begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd6; end
6'b000011 : //3
begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd6; end
6'b000100 : //4
begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd7; end
6'b000101 : //5
begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd7; end
6'b000110 : //6
begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd8; end
6'b000111 : //7
begin  vlcode_ac1 <= {17'b00000000000000100,rl_in[11]}; codelength_ac1 <= 5'd8; end
6'b001000 : //8
begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd8; end
6'b001001 : //9
begin  vlcode_ac1 <= {17'b00000000001111000,rl_in[11]}; codelength_ac1 <= 5'd8; end
6'b001010 : //10
begin  vlcode_ac1 <= {17'b00000000001111010,rl_in[11]}; codelength_ac1 <= 5'd8; end
6'b001011 : //11
begin  vlcode_ac1 <= {17'b00000000000100001,rl_in[11]}; codelength_ac1 <= 5'd9; end
6'b001100 : //12
begin  vlcode_ac1 <= {17'b00000000000100101,rl_in[11]}; codelength_ac1 <= 5'd9; end
6'b001101 : //13
begin  vlcode_ac1 <= {17'b00000000000100100,rl_in[11]}; codelength_ac1 <= 5'd9; end
6'b001110 : //14
begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd10; end
6'b001111 : //15
begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd10; end
6'b010000 : //16
begin  vlcode_ac1 <= {17'b00000000000001101,rl_in[11]}; codelength_ac1 <= 5'd11; end
endcase
end

/***************************************************************************************/

{1'b0,6'b000000,11'bx}: // scan type = 0, run = 0, level = x
begin
case ({1'b0,rl_in[10:0]}) //(level)
12'b000000000010 : //2
begin  vlcode_ac1 <= {17'b00000000000000100,rl_in[11]}; codelength_ac1 <= 5'd5; end
12'b000000000011 : //3
begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd6; end
12'b000000000100 : //4
begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd8; end
12'b000000000101 : //5
begin  vlcode_ac1 <= {17'b00000000000100110,rl_in[11]}; codelength_ac1 <= 5'd9; end
12'b000000000110 : //6
begin  vlcode_ac1 <= {17'b00000000000100001,rl_in[11]}; codelength_ac1 <= 5'd9; end
12'b000000000111 : //7
begin  vlcode_ac1 <= {17'b00000000000001010,rl_in[11]}; codelength_ac1 <= 5'd11; end
12'b000000001000 : //8
begin  vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd13; end
12'b000000001001 : //9
begin  vlcode_ac1 <= {17'b00000000000011000,rl_in[11]}; codelength_ac1 <= 5'd13; end
12'b000000001010 : //10
begin  vlcode_ac1 <= {17'b00000000000010011,rl_in[11]}; codelength_ac1 <= 5'd13; end
12'b000000001011 : //11
begin  vlcode_ac1 <= {17'b00000000000010000,rl_in[11]}; codelength_ac1 <= 5'd13; end
12'b000000001100 : //12
begin  vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd14; end
12'b000000001101 : //13
begin  vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd14; end
12'b000000001110 : //14
begin  vlcode_ac1 <= {17'b00000000000011000,rl_in[11]}; codelength_ac1 <= 5'd14; end
12'b000000001111 : //15
begin  vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd14; end
endcase
end

/***************************************************************************************/

{1'b1,6'b000000,11'bx}: // scan type = 1, run = 0, level = x
begin
case ({1'b0,rl_in[10:0]}) //(level)
12'b000000000001 : //1
begin  vlcode_ac1 <= {17'b00000000000000010,rl_in[11]}; codelength_ac1 <= 5'd3; end
12'b000000000010 : //2
begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd4; end
12'b000000000011 : //3
begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd5; end
12'b000000000100 : //4
begin  vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd6; end
12'b000000000101 : //5
begin  vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd6; end
12'b000000000110 : //6
begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd7; end
12'b000000000111 : //7
begin  vlcode_ac1 <= {17'b00000000000000100,rl_in[11]}; codelength_ac1 <= 5'd7; end
12'b000000001000 : //8
begin  vlcode_ac1 <= {17'b00000000001111011,rl_in[11]}; codelength_ac1 <= 5'd8; end
12'b000000001001 : //9
begin  vlcode_ac1 <= {17'b00000000001111100,rl_in[11]}; codelength_ac1 <= 5'd8; end
12'b000000001010 : //10
begin  vlcode_ac1 <= {17'b00000000000100011,rl_in[11]}; codelength_ac1 <= 5'd9; end
12'b000000001011 : //11
begin  vlcode_ac1 <= {17'b00000000000100010,rl_in[11]}; codelength_ac1 <= 5'd9; end
12'b000000001100 : //12
begin  vlcode_ac1 <= {17'b00000000011111010,rl_in[11]}; codelength_ac1 <= 5'd9; end
12'b000000001101 : //13
begin  vlcode_ac1 <= {17'b00000000011111011,rl_in[11]}; codelength_ac1 <= 5'd9; end
12'b000000001110 : //14
begin  vlcode_ac1 <= {17'b00000000011111110,rl_in[11]}; codelength_ac1 <= 5'd9; end
12'b000000001111 : //15
begin  vlcode_ac1 <= {17'b00000000011111111,rl_in[11]}; codelength_ac1 <= 5'd9; end
endcase
end

/***************************************************************************************/

{1'b0,6'bx,11'b00000000010}: // scan type = 0, run = x, level = 2
begin
case ({1'b0,rl_in[10:0]}) //(level)
12'b000000000001 : //1
begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd7; end
12'b000000000010 : //2
begin  vlcode_ac1 <= {17'b00000000000000100,rl_in[11]}; codelength_ac1 <= 5'd8; end
12'b000000000011 : //3
begin  vlcode_ac1 <= {17'b00000000000100100,rl_in[11]}; codelength_ac1 <= 5'd9; end
12'b000000000100 : //4
begin  vlcode_ac1 <= {17'b00000000000001111,rl_in[11]}; codelength_ac1 <= 5'd11; end
12'b000000000101 : //5
begin  vlcode_ac1 <= {17'b00000000000001001,rl_in[11]}; codelength_ac1 <= 5'd11; end
endcase
end

/***************************************************************************************/

{1'b1,6'bx,11'b00000000010}: // scan type = 1, run = x, level = 2
begin
case ({1'b0,rl_in[10:0]}) //(level)
12'b000000000001 : //1
begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd6; end
12'b000000000010 : //2
begin  vlcode_ac1 <= {17'b00000000000001110,rl_in[11]}; codelength_ac1 <= 5'd8; end
12'b000000000011 : //3
begin  vlcode_ac1 <= {17'b00000000000100110,rl_in[11]}; codelength_ac1 <= 5'd9; end
12'b000000000100 : //4
begin  vlcode_ac1 <= {17'b00000000011111101,rl_in[11]}; codelength_ac1 <= 5'd9; end
12'b000000000101 : //5
begin  vlcode_ac1 <= {17'b00000000000000100,rl_in[11]}; codelength_ac1 <= 5'd10; end
endcase
end

/***************************************************************************************/

{1'bx,6'b000010,11'b00000000101}: // scan_type = 0, EOB
begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd14; end
{1'bx,6'b000010,11'b00000000101}: // scan type = x, run = 2, level = 5
begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd14; end
{1'bx,6'b000010,11'b00000000101}: // scan type = x, run = 2, level = 5
begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd14; end
{1'bx,6'b000010,11'b00000000101}: // scan type = x, run = 2, level = 5
begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd14; end
{1'bx,6'b000010,11'b00000000101}: // scan type = x, run = 2, level = 5
begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd14; end
{1'bx,6'b000010,11'b00000000101}: // scan type = x, run = 2, level = 5
begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd14; end

default:
begin  vlcode_ac1 <= rl_in; codelength_ac1 <= 5'd18; end

endcase
end
end

/*****************************************************************************/

/* pipeline vlcode_ac1 and codelength_ac1 to match the 2 pipe stages of the
corresponding DC values */

always @ (posedge CLK)
if (RST)
begin
vlcode_ac <= {18'b0}; codelength_ac <= 5'd0;
end
else
begin
vlcode_ac <= vlcode_ac1; codelength_ac <= codelength_ac1;
end

/*****************************************************************************/

/* select code and codelength. Counter value set at 2 because of the 2 pipestages
od the AC and DC codelengths and vl codes */

always @ (posedge CLK or posedge RST)
begin
if (RST)
begin
codelength1 <= 5'b0;  vlcode1 <= 18'b0;
end
else if (rdy_in == 1'b1 & cntr64 == 7'b0000010)
begin
codelength1 <= {1'b0,codelength_dc};
vlcode1 <= {8'b0,vlcode_dc};
end
else
begin
codelength1 <= codelength_ac;
vlcode1 <= {vlcode_ac};
end
end

/*****************************************************************************/

/* pipeline code and codelength. This is done to match the pipestages with
cl_sum_prev which is multiplied with vlcode. */

always @ (posedge CLK or posedge RST)
begin
if (RST)
begin
codelength2 <= 5'b0;
vlcode2 <= 18'b0; vlcode3 <= 18'b0;vlcode4 <= 18'b0;
end
else if (rdy_in == 1'b1)
begin
codelength2 <= codelength1;
vlcode2 <= vlcode1; vlcode3 <= vlcode2;vlcode4 <= vlcode3;
end
end

/*****************************************************************************/
/* The maximum length of the vlc code can be 18 bits + 6 bits = 24 bits. This happens
when a run level pair not defined in the table is encountered. In this case , a 6 bit
escape code followed by 6 bit run code and 12 bit level code is used.  The minimum
length of the vlc code is 2 bits. This happens when encoding an "EOB" symbol. After
finding the vlc code for a particular run/level pair, the code is shifted into a
barrel shifter.

Every time there are 16 bits in the barrel shifter, the contends of the shifter is
enabled out as the huffman_out signal. Each run length value is read in and the corresponding
vlc code is found out (vlcode_dc or vlcode_ac1). For each code, the codelength is also
stored in a ROM. The codelengths are added up (cl_sum) and when it reaches 16 or 32,
the code is sent out.

The maximum  value for cl_sum happens when a 15 bit code is followed by a 24 bit
code. So the max. value for cl_sum is 15 + 24 = 39. The barrel shifter has 39 valid
registers. For ease of coding, 48 (3 * 16) registers are used. These registers are
divided into upper_reg, middle_reg and lower_reg. Each time upper_reg if full (ie.,
16 or more bits in barrel shifter), the contends are sent out. The remaining bits
, if any, in the middle_reg are moved up to the upper_reg. If the barrel shifter
has 32 or more valid data, the upper and middle registers are full and the upper
reg data is sent out followed by the middle reg data. The remaining bits, if any
in the lower register is moved up to the upper register.*/

/*****************************************************************************/
/* calculate sum of codelength. set half flag and full flag . Half flags indicates
that the upper_reg is full and full flag indicates that the lower register is full.
cl_sum_prev gives the sum of the codelengths which is used to set the flags. cl_sum
is used to find out the number of shifts to be done in the barrel shifts.*/

always @ (posedge CLK or posedge RST)
begin
if (RST)
begin
cl_sum <= 6'b100111; cl_sum_prev <= 6'b0;
half_flag1 <= 1'b0; full_flag1 <= 1'b0;
end
else if ( cl_sum_rdy == 1'b1)
begin
if (cl_sum_prev < 6'd16)
begin
cl_sum_prev <= codelength1 + cl_sum_prev;
cl_sum <= (6'b100111 - cl_sum_prev);
half_flag1 <= 1'b0;
full_flag1 <= 1'b0;
end
else if (cl_sum_prev <= 6'd32 && cl_sum_prev >= 6'd16)
begin
cl_sum_prev <= codelength1 + (cl_sum_prev - 5'b10000);
cl_sum <= (6'b100111 - cl_sum_prev);
half_flag1 <= 1'b1;
full_flag1 <= 1'b0;
end
else if (cl_sum_prev >= 6'd32)
begin
cl_sum_prev <= codelength1 + (cl_sum_prev - 6'b100000);
cl_sum <= (6'b100111 - cl_sum_prev);
half_flag1 <= 1'b1;
full_flag1 <= 1'b1;
end
end
end

/*****************************************************************************/

/* barrel shifting done using multiplier. Barrel shifting coefficients are
stored in a ROM and selected depending on the value of cl_sum */

always @ (posedge CLK)
begin
if (RST)
begin
cl_sum_shift <= 39'b0;
end
else
begin
case (cl_sum)
6'd0 : begin cl_sum_shift <=  39'b000000000000000000000000000000000000000; end
6'd1 : begin cl_sum_shift <=  39'b000000000000000000000000000000000000010; end
6'd2 : begin cl_sum_shift <=  39'b000000000000000000000000000000000000100; end
6'd3 : begin cl_sum_shift <=  39'b000000000000000000000000000000000001000; end
6'd4 : begin cl_sum_shift <=  39'b000000000000000000000000000000000010000; end
6'd5 : begin cl_sum_shift <=  39'b000000000000000000000000000000000100000; end
6'd6 : begin cl_sum_shift <=  39'b000000000000000000000000000000001000000; end
6'd7 : begin cl_sum_shift <=  39'b000000000000000000000000000000010000000; end
6'd8 : begin cl_sum_shift <=  39'b000000000000000000000000000000100000000; end
6'd9 : begin cl_sum_shift <=  39'b000000000000000000000000000001000000000; end
6'd10 : begin cl_sum_shift <= 39'b000000000000000000000000000010000000000; end
6'd11 : begin cl_sum_shift <= 39'b000000000000000000000000000100000000000; end
6'd12 : begin cl_sum_shift <= 39'b000000000000000000000000001000000000000; end
6'd13 : begin cl_sum_shift <= 39'b000000000000000000000000010000000000000; end
6'd14 : begin cl_sum_shift <= 39'b000000000000000000000000100000000000000; end
6'd15 : begin cl_sum_shift <= 39'b000000000000000000000001000000000000000; end
6'd16 : begin cl_sum_shift <= 39'b000000000000000000000010000000000000000; end
6'd17 : begin cl_sum_shift <= 39'b000000000000000000000100000000000000000; end
6'd18 : begin cl_sum_shift <= 39'b000000000000000000001000000000000000000; end
6'd19 : begin cl_sum_shift <= 39'b000000000000000000010000000000000000000; end
6'd20 : begin cl_sum_shift <= 39'b000000000000000000100000000000000000000; end
6'd21 : begin cl_sum_shift <= 39'b000000000000000001000000000000000000000; end
6'd22 : begin cl_sum_shift <= 39'b000000000000000010000000000000000000000; end
6'd23 : begin cl_sum_shift <= 39'b000000000000000100000000000000000000000; end
6'd24 : begin cl_sum_shift <= 39'b000000000000001000000000000000000000000; end
6'd25 : begin cl_sum_shift <= 39'b000000000000010000000000000000000000000; end
6'd26 : begin cl_sum_shift <= 39'b000000000000100000000000000000000000000; end
6'd27 : begin cl_sum_shift <= 39'b000000000001000000000000000000000000000; end
6'd28 : begin cl_sum_shift <= 39'b000000000010000000000000000000000000000; end
6'd29 : begin cl_sum_shift <= 39'b000000000100000000000000000000000000000; end
6'd30 : begin cl_sum_shift <= 39'b000000001000000000000000000000000000000; end
6'd31 : begin cl_sum_shift <= 39'b000000010000000000000000000000000000000; end
6'd32 : begin cl_sum_shift <= 39'b000000100000000000000000000000000000000; end
6'd33 : begin cl_sum_shift <= 39'b000001000000000000000000000000000000000; end
6'd34 : begin cl_sum_shift <= 39'b000010000000000000000000000000000000000; end
6'd35 : begin cl_sum_shift <= 39'b000100000000000000000000000000000000000; end
6'd36 : begin cl_sum_shift <= 39'b001000000000000000000000000000000000000; end
6'd37 : begin cl_sum_shift <= 39'b010000000000000000000000000000000000000; end
6'd38 : begin cl_sum_shift <= 39'b100000000000000000000000000000000000000; end
default : begin cl_sum_shift <= 39'b000000000000000000000000000000000000000; end
endcase
end
end

/*****************************************************************************/
/* multiplier used to do barrel shifting of codeword. flags pipeleined to match
the pipe line stages of upper, middle and lower registers. */

always @ (posedge CLK or posedge RST)
begin
if (RST)
begin
mult_out <= 39'b0;
full_flag2 <= 1'b0; half_flag2 <= 1'b0;
full_flag3 <= 1'b0; half_flag3 <= 1'b0;
full_flag4 <= 1'b0; half_flag4 <= 1'b0;
full_flag5 <= 1'b0; half_flag5 <= 1'b0;
full_flag6 <= 1'b0;
end
else if (rdy_in == 1'b1)
begin
mult_out <= vlcode4 * cl_sum_shift;
full_flag2 <= full_flag1; half_flag2 <= half_flag1;
full_flag3 <= full_flag2; half_flag3 <= half_flag2;
full_flag4 <= full_flag3; half_flag4 <= half_flag3;
full_flag5 <= full_flag4; half_flag5 <= half_flag4;
full_flag6 <= full_flag5;
end
end

/*****************************************************************************/
always @ (posedge CLK or posedge RST)
begin
if (RST)
begin
upper_reg1 <= 16'b0; middle_reg1 <= 16'b0; lower_reg1 <= 16'b0;
end
else if (rdy_in == 1'b1)
begin
case({full_flag4, half_flag4})
2'b00: begin upper_reg1[16:1] <= mult_out[38:23] | upper_reg1[16:1];
middle_reg1 <= mult_out[22:7] ;
lower_reg1 <= {mult_out[6:0],9'b0 }; end
2'b01: begin upper_reg1[16:1] <= mult_out[38:23] | middle_reg1[16:1];
middle_reg1 <= mult_out[22:7];
lower_reg1 <= {mult_out[6:0],9'b0}; end
2'b11: begin upper_reg1 <= mult_out[38:23] | lower_reg1;
middle_reg1 <= mult_out[22:7];
lower_reg1 <= {16'b0}; end
default:begin upper_reg1 <= upper_reg1;
middle_reg1 <= middle_reg1;
lower_reg1 <= lower_reg1; end
endcase
end
end

/*****************************************************************************/

always @ (posedge CLK or posedge RST)
begin
if (RST)
begin
upper_reg2 <= 16'b0; middle_reg2 <= 16'b0;
middle_reg3 <= 16'b0;
end
else if (rdy_in == 1'b1)
begin
upper_reg2 <= upper_reg1;
middle_reg2 <= middle_reg1;
middle_reg3 <= middle_reg2;

end
end

/*****************************************************************************/

always @ (posedge CLK or posedge RST)
begin
if (RST)
begin
huffman_out <= 16'b0;
end
else if (rdy_in == 1'b1)
begin
if (half_flag5 == 1'b1)
huffman_out <= upper_reg2;
else if (full_flag6 == 1'b1)
huffman_out <= middle_reg3;
end
end

/*****************************************************************************/

/* counter that counts upto 64. */

always @ (posedge CLK or posedge RST)
begin
if (RST)
begin
cntr64 <= 7'b1000000;
end
else if (rdy_in == 1'b1)
begin
if (cntr64 < 7'b1000000)
cntr64 <= cntr64 + 1;
else
cntr64 <= 7'b0000001;
end
end

/* cl_sum starts after 2 clks from reset. */

always @ (posedge CLK or posedge RST)
begin
if (RST)
begin
cl_sum_rdy <= 1'b0;
end
else
begin
if (cntr64 == 7'b0000010)
cl_sum_rdy <= 1'b1;
else
cl_sum_rdy <= cl_sum_rdy;
end
end
/*****************************************************************************/

/* counter that counts upto 64. */

always @ (posedge CLK or posedge RST)
begin
if (RST)
begin
rdy_out <= 1'b0;
end
else if (rdy_in == 1'b1)
begin
rdy_out <= 1'b1;
end
end

/*****************************************************************************/
endmodule

]]> http://blog.ektel.com.np/2012/04/huffman-encoder-verilog-hdl-code/feed/ 0 Dowload Xilinx EDA software for free http://blog.ektel.com.np/2012/04/dowload-xilinx-eda-software-for-free/?utm_source=rss&utm_medium=rss&utm_campaign=dowload-xilinx-eda-software-for-free http://blog.ektel.com.np/2012/04/dowload-xilinx-eda-software-for-free/#comments Sun, 15 Apr 2012 15:36:48 +0000 admin http://blog.ektel.com.np/?p=334 Here I want to share download link for Xilinx ISE 13.4 for free. Xilinx is one of the most popular EDA software that is used by professional engineers and companies to produce VLSI FPGA architecture design, optimization and prototyping. The Xilinx software is one of the most expensive EDA software and it's competitor FPGA vendor is Altera. With Xilinx you can do all kinds of electronics design using logic gates and optimize the logic gates for power, speed and area. As an example you can create simple counter, multiplexer, encoder, adder, subtractor and use those building blocks to model real application electronic system such as mobile handset or router or switches or modulator/demodulator.Video encoder/decoder such as Mpeg-2 encoder/decoder, MPeg4 encoder/decoder, LTE advanced system can also be build with Xilinx. See below for the free download link for Xilinx. There are lots of other things you can do. Xilinx is compactible with MATLAB so that you can do simulation in MATLAB and optimize it on Xilinx or vice versa. You can create systematic map which shows you all the interconnected gates. After that you can do VLSI architecture design and optimization.

Here is the free download link for Xilinx,

http://www.netload.in/datei6nf5D9iOE3/tbex134l.part06.rar.htm

http://www.netload.in/dateiBFRo4tK8Lz/tbex134l.part05.rar.htm

http://www.netload.in/datei3kJxBY7UFV/tbex134l.part04.rar.htm

http://www.netload.in/dateiOZ1HJl7FoE/tbex134l.part03.rar.htm

http://www.netload.in/dateizePIcgC66Q/tbex134l.part02.rar.htm

http://www.netload.in/dateiYD8XnP3W3U/tbex134l.part01.rar.htm

http://www.netload.in/dateiVb7pdiyWiQ/tbex134l.part12.rar.htm

http://www.netload.in/dateirCTQQbex3n/tbex134l.part11.rar.htm

http://www.netload.in/dateilcuH20i6PE/tbex134l.part10.rar.htm

http://www.netload.in/dateiX0IlSyPxXp/tbex134l.part09.rar.htm

http://www.netload.in/dateiMYqGmGex5p/tbex134l.part08.rar.htm

http://www.netload.in/datei8hA8KQw9At/tbex134l.part07.rar.htm

If the free download link for Xilinx does not work please contact me

You can read more below:

]]> http://blog.ektel.com.np/2012/04/dowload-xilinx-eda-software-for-free/feed/ 0 VLSI Architecture and Design for MPEG Encoder Decoder http://blog.ektel.com.np/2012/03/vlsi-architecture-and-design-for-mpeg-encoder-decoder/?utm_source=rss&utm_medium=rss&utm_campaign=vlsi-architecture-and-design-for-mpeg-encoder-decoder http://blog.ektel.com.np/2012/03/vlsi-architecture-and-design-for-mpeg-encoder-decoder/#comments Wed, 21 Mar 2012 08:41:10 +0000 admin http://blog.ektel.com.np/?p=311 This article is about the design of source encoder and decoder using Huffman algorithm that are widely used today, eg MPEG Encoder. First systematic block diagram of essential components such as Discrete Fourier Transform(DCT), Run Length encoder, Huffman Encoder are  explained. Note that decoder are same and only encoder are different manufactured by different companies. Next the verilog and vhdl codes are obtained for the block diagram components and then xilinx eda software is used to simulate and synthesis the HDL codes to obtain encoder schematic layout, gate level design schematic showing functional units. Final output is FPGA VLSI electronic processor for source encoder based on Huffman algorithm to compress the input signal. This design is itself a small part of communication system which includes LPF, source encoding, channel encoding, modulation of the signal.

VLSI Architecture and Design for MPEG Encoder Decoder

The encoder uses 3 functional blocks as:

  1. Zigzag encoder
  2. Run Length Encoder(RLE)
  3. Variable Length Encoder (Huffman Encoder)

This is illustrated below:

variable length encoder

Fig: Variable Length Encoder

1. Zigzag encoder

The input to the Zigzag encoder is the quantized DCT coefficients (DC and AC coefficient). The DCT coefficient are produced by applying Discrete Fourier Transform to the 8 by 8 block input pixel. These quantized DCT coefficients will have non-zero low frequency components in the top left corner of the 8×8 block and higher frequency components in the remaining places. The higher frequency components approximate to zero after quantization. The low frequency DCT coefficients are more important than higher frequency DCT coefficients. Even if we ignore some of the higher frequency coefficients, we can successfully reconstruct the image from the low frequency coefficients only. The zigzag scanner scans the DCT coefficients input in zigzag manner as shown in the figure below:

zigzag scanner for MPEG

Fig: ZigZag Scanner

The reason for applying Zigzag scan on the DC coefficient is to put the high frequency components together. The output of the zigzag scanner is thus strings of quantized DC coefficients with DC first and then high frequency AC components. The Zigzag scan block diagram is shown below:

zigzag scanner block diagram

Fig: zigzag scanner block diagram

2. Run Length Encoder(RLE):

The Run Length Encoder works by recording runs of same input symbol as  the the symbol and its count. For eg., if input is "a a a a b b c c c c c c....." then Run Length Encoder would result "4a2b6c"etc. Here a, b, c would be level and 4,2,6 would be runs. Thus the output of the RLE is run/level combination.

The general block diagram and internal architecture block diagram of Run Length Encoder is shown below:

Block Diagram of Run Length Encoder

Fig: Block Diagram of Run Length Encoder

Internal Architecture of Run Length Encoder

Fig: Internal Architecture of Run Length Encoder

 

 

 

3. Huffman Encoder/ Decoder:

The output of the run length encoder is fed into Huffman Encoder. Each of the Run/Level input is assigned variable length codes such that the high probability run/level is assigned small codes and low probability run/level larger codes. This conversion table or lookup table is maintained in both the Encoder and Decoder and implemented as ROM.

The block diagram of the Huffman Encoder are shown below:

General Block Diagram of Huffman Encoder

Huffman Encoder

Fig: Huffman Encoder

 

Inside Huffman Encoder

Fig: Inside Huffman Encoder

The VLSI architecture of Huffman Encoder/Decoder is shown below:

vlsi architecture of huffman encoder-decoder

Fig: VLSI architecture of huffman encoder-decoder

 

The verilog HDL and VHDL codes for the mpeg encoder based on huffman encoding is below for downloads:

Go to Next Section

  1. Huffman encoder Verilog code
  2. Huffman encoder VHDL code
  3. Huffman encoder VLSI systematic block  diagram

Decoder essential performs the reverse algorithm of the source encoder algorithm. In this case the decoding algorithm is performed using decoding tables which is the same as the encoder table wherein different signal amplitude level is assigned variable length codes. This conversion table is maintained in the decoder circuits as said before, to get back the signal amplitude and hence the video or audio or both signal as used in mpeg encoder

]]> http://blog.ektel.com.np/2012/03/vlsi-architecture-and-design-for-mpeg-encoder-decoder/feed/ 0 ITU-T recommendation for telephone numbering plan for PSTN http://blog.ektel.com.np/2012/03/itu-t-recommendation-for-telephone-numbering-plan-for-pstn/?utm_source=rss&utm_medium=rss&utm_campaign=itu-t-recommendation-for-telephone-numbering-plan-for-pstn http://blog.ektel.com.np/2012/03/itu-t-recommendation-for-telephone-numbering-plan-for-pstn/#comments Sat, 17 Mar 2012 11:53:33 +0000 admin http://blog.ektel.com.np/?p=306 As of now, ITU-T recommends E.164 standard for the telephone numbering plan for the PSTN. Rec E.164 defines use of prefix "+" for international call followed by 15 digits. The 15 digits includes country code(cc), the national destination code(NDC) and the subscriber number. The national destination code(NDC) refers to the combination of the area code and the exchange code. Exchange code is the code number of the PSTN switch.

The following different codes makes up telephone number.

  1. Country cod
  2.  National Destination Code (NDC)
  3. Subscriber Number

1. Country Code:

Country code are assigned for each country for identification purpose. This can be of 1 digit to 3 digit long. The country codes are assigned based on 9 zones as follows:
Zone 1: North America(eg, for US or Canada, +1)
Zone 2: Africa (eg, +216 for Tunisia)
Zone 3/4: Europe(eg, +30 for Greece)
Zone 5: South America(eg, +54 Argentine)
Zone 6: South East Asia and Oceania(eg, +61 for Australia)
Zone 7: Eurasia(eg, +7 for Russia)
Zone 8: East Asia(eg, +86 for China)
Zone 9: Central,South,Western Asia(eg, +977 for NEpal)

2. National Destination Code(NDC):
Area code and exchange code together forms the national destination code
a. Area Code:
A country is usually divided into districts and/or zones. Each of which is given an area code(for example Kathmandu is 1, whereas Dharan is 25).
b. Exchange Code:
An area may contain several exchanges and to identify them exchange code is assigned to them.
3. Subscriber Number:
The number given to a subscriber telephone line is called subscriber number.

]]> http://blog.ektel.com.np/2012/03/itu-t-recommendation-for-telephone-numbering-plan-for-pstn/feed/ 0 CBRT System implementation within IN(Intelligent Network) http://blog.ektel.com.np/2012/02/cbrt-system-implementation-within-inintelligent-network/?utm_source=rss&utm_medium=rss&utm_campaign=cbrt-system-implementation-within-inintelligent-network http://blog.ektel.com.np/2012/02/cbrt-system-implementation-within-inintelligent-network/#comments Sat, 18 Feb 2012 07:35:01 +0000 admin http://blog.ektel.com.np/?p=285 CRBT(Color Ring Back Tone) is a Telecommunication VAS in which the caller can hear songs tune if the called party has CRBT enabled.

This article explains how CRBT operates within the Intelligent Network architecture. The MSC (or SSP) must support the CAMEL Application Part(CAP) Phase 4 (or INAP CS2). The MSCs, SCPs and IPs are all interconnected as shown in the figure. The IPs(Intelligent Peripherals) are responsible for playing the CRBT tunes as directed by the SCP. The IN has separate SCPs dedicated for CRBT. The number of SCP depends on the number of mobile subscriber the Network Operator has, that is it is subject to capacity. The SCPs(Service Control Points) function is to co-ordinate the call, check the whether the dialed number has CRBT feature enabled by inquiring the HLR, directing IP to play the CRBT and other functions.

Consider a mobile subscriber A who is calling a subscriber B. Let the subscriber B has CRBT service so that when subscriber A calls subscriber B, subscriber A hears subscriber CRBT song. Let us also consider that subscriber A is handled by MSC A and subscriber B is handled by MSC B.

The CRBT signal flow animation is shown below: Click to see the Animation

CBRT System implementation within IN(Intelligent Network)

Fig: CBRT System implementation within IN(Intelligent Network) Animation

The steps are as follows;

1. The subscriber A makes a call, which is received by the MSC A. MSC A sends an IAM(Initial Address Message) to SCP which triggers the SCPs for making service status checks for the number.

2. The SCP processes the data received from MSC A. It makes inquiry to HLR(database) to check whether the dialed number has CRBT service provisioned or not.

3. At the same time, the SCP sends ICA(Initiate Call Attempt) message to MSC A, instructing MSC A to make an outgoing call to the called party. That is it instructs MSC A to connect to MSC B to make temporal ordinary phone call.

4. To make the outgoing call, MSC A connects to MSC B(because subscriber B is handled by MSC B). This call flow is called the Leg 2. This signal is monitored by the SCP so that it knows the status of the call(ringing, answered, busy).

5.  The MSC B sends reply to MSC A with the ACM(Address Complete Message). Path from subscriber A to subscriber B is now connected. The call can be ringing tone or busy tone.

6. The subscriber B phone starts to ring, and the MSC A notifies SCP about this ringing status by sending ERB (Event Reprot BCSM) message. BCSM stands for Basic Call State Machine.

7. After receiving the ringing status from MSC A, SCP replies to MSC A by sending ETC(Establish Temporary Connection) message that instructs MSC A to connect to the IP(Intelligent Peripheral) temporarily.

8.  MSC A connects to the IP by communicating messages between as follows: MSC A sends ISUP IAM to IP, the IP responds by sending ACM followed by  ANM message. Now IP is connected to MSC A.

9. Once the IP and MSC A are connected, IP sends ARI(Assist Request Instruction) message to the SCP that ask SCP what CRBT tune to play. The SCP responds by sending PA(Play Announcement) message to IP, instructing IP which CRBT tune to play.

Now the subscriber A is connected to the IP via MSC A and can hear CRBT tone. This path is known as Leg1. The other path connection from MSC A to MSC B which is still active and in normal ringing tone is called Leg 2 and due to this the called party hears a normal call tone. This leg 2 is being monitored by the SCP to know the status of the call.

10. Once the subscriber B answers the call, MSC B sends the MSC A an ANM message notifying MSC A that called party has answered the phone.

11. Now the MSC A notifies SCP that the called party(subscriber B) has answered the call by sending ERB message. This is leg 2 answer.

12. Now the SCP has to disconnect the CRBT connection(leg1) between subscriber A (via MSC A) and IP. This is done as follows; SCP sends MSC A a DFCWA(Disconnect Forward Connection With Argument) message instructing MSC A to disconnect its connection to IP. The MSC A upon receiving this message sends a REL(Release) message to the IP to disconnect the trunk lines between them. IP notifies the MSC A to acknowledge this by sending RLC message.

Now the connection between MSC A and IP is disconnected.

13. Finally SCP sends MOVEleg message to the MSC A. This is initiated to join the two legs.  The MSC A replies to SCP with MOVEleg return result message. This causes the two signalling legs to be joined and the subscriber A and B are now connected directly with normal speech path.

 

]]> http://blog.ektel.com.np/2012/02/cbrt-system-implementation-within-inintelligent-network/feed/ 0 SMSC SMPP Server http://blog.ektel.com.np/2012/01/smsc-smpp-server/?utm_source=rss&utm_medium=rss&utm_campaign=smsc-smpp-server http://blog.ektel.com.np/2012/01/smsc-smpp-server/#comments Fri, 06 Jan 2012 21:50:35 +0000 admin http://blog.ektel.com.np/?p=248 SMPP(Short Message Peer to Peer) is a standardized protocol that handles the communication between SMSC and other SMS entities. It is an interface between the SMSC and NON-PLMN SMEs ( Short Message Entity). Typically it specifies the interface used between the SMSC and ESME ( External Short Message Entity) systems. This SMPP protocol may be implemented over a variety of underlying communications protocols  X.25 or TCP/IP over internet or leased line by pluging in the IP cables into the SMPP server and opening the correct SMPP port.

The diagram below shows how ESME is connected to the SMSC via the SMPP server (SMPP gateway).

ESME to SMSC Interconnection

Fig: ESME to SMSC Interconnection (click to enlarge)

The SMPP Agent (process) is responsible for maintaining the communication link with the ESME, accomplishing the conversion of the SMPP standard message and the internal message of the SMSC ( Short Message Service Centre ) system, and providing the external short message entity (ESME) with the open interface to access the SMSC system. The current version of SMPP protocol is 3.4  (SMPP3.4).

As explained in the communication between ESME and SMSC servers post, there are two transmission modes between ESME and SMSC servers, namely-

  1. Transmitter Mode
  2. Receiver Mode

The following diagram explains the role of SMPP server during the connection establishment and release between the ESME server and SMS server

Transmission Mode:

Role of SMPP server during transmission mode

Fig: Role of SMPP server during transmission mode(click to enlarge)

In the figure,

•Steps (1)  to (4): ESME is bound with SMSC in transmitter mode, so that short messages can be sent to SMSC;
•Steps (5) to (8): ESME submits short messages to SMSC;
•Steps (9) to (10): ESME sends link detection messages to SMPP AGENT.
•Steps (11) to (14): Disconnect the link between ESME and SMSC.
Receiver Mode:
Role of SMPP server in Receiver Mode

Fig: Role of SMPP server in Receiver Mode(Click to Enlarge)

In the figure:

•Steps (1) to (4): ESME is bound with SMSC in Receiver mode and is ready to receive short messages from SMSC;
•Steps (5) to (8): SMSC distributes a short message to ESME.
•Steps (9) to  (12): Disconnect the link between ESME and SMSC.
The SMPP server and/or SMPP gateway is usually used in cluster mode, meaning that it has two same processor(active and standby) such that when one is down the other will be automatically turned on. Thus it has two IP address for each server processor and one floating IP for identification as single SMPP server and/or SMPP gateway. The server may run on Windows servers or linux servers. SMPP client is required on the ESME server side if there is need of SMS server. To connect to the ESME server to SMPP server the SMPP port number, username, password and SMS shortcode are required.
More on
]]> http://blog.ektel.com.np/2012/01/smsc-smpp-server/feed/ 0 SMS Messages between ESME Server and SMSC Server http://blog.ektel.com.np/2012/01/sms-messages-between-esme-server-and-smsc-server/?utm_source=rss&utm_medium=rss&utm_campaign=sms-messages-between-esme-server-and-smsc-server http://blog.ektel.com.np/2012/01/sms-messages-between-esme-server-and-smsc-server/#comments Fri, 06 Jan 2012 15:19:37 +0000 admin http://blog.ektel.com.np/?p=231 This article explains the processes involved during sms messaging from a ESME server to the SMSC server. This helps in understanding the underlying sms messaging concept which can be applied to design of ESME. First the meaning of elementary components are explained.

ESME(External Short Message Entity) is the name given to SMS Server(s) or SMS provider external to the SMS service provider network. Usually ESME server are owned by private business companies or government organizations that use SMS messaging service to provide various sms application such as Mobile Commerce(advertising), Mobile Banking by Banks, Email gateway (where email is send to sms gateway), notification applications, directory services, telemetry, vehicle tracking, cell broadcast etc. On the other hand, the SMSC server/ SMS server are usually owned by telecommunication or mobile operators (owning to the fact of  SMSC cost and operation cost). Both Entities are known as SMS provider but the telecommunication company or mobile operators are usually the sms gateway provider. SMS Short Codes or just short codes are given to ESME owners by the SMSC owners for identification purpose and connection between the ESME and SMSC servers. Multiple ESME servers can be connected to SMSC via SMS gateway. SMS gateway of SMSC is also the gateway for sending international SMS. The interconnection of SMSC with MSC and HLR is shown in this SMSC post. The status of the connections between the multiple ESME servers and SMSC can be viewed at the SMSC location. The connection between the ESME servers and SMSC server is such that, ESME server is connected TCP/IP or X.25 network (internet or leased line). The TCP/IP or X.25 network is connected to the SMPP server and then SMPP server is connected to the SMSC server. This is illustrated in figure below.

  • Method of the ESME to access the SMSC
ESME and SMSC Communication

Fig: ESME and SMSC Communication

In order to design ESME, the ESME interface must support TCP/IP and/or X.25 networking capabilities.  The software part of ESME must be capable of executing the following modes of transmission.

Interworking between the SMSC and ESMEs are categorised as:

  1. Messages from ESMEs to the SMSC
  2. Messages from SMSC to ESMEs
  • Transmission mode between ESME and SMSC

There are two transmission mode between ESMS and SMSC

  1. Transmitter Mode
  2. Receiver Mode

1. Transmitter Mode

In transmitter binding mode, the ESME binds with the SMSC as a transmitter. When the binding is successful, the ESME can initiate messages to the SMSC. For example, the ESME can transmit to the SMSC submit_sm, query_sm, cancel_sm, replace_sm, enquire_link and other messages.
2. Receiver Mode
In this mode, the ESME binds with the SMSC as a receiver. When the binding is successful, the ESME can receive messages initiated by the SMSC. SMSC can send a deliver_sm message to ESME.
  • Message Types
Messages between ESME and SMSC

Fig: Messages between ESME and SMSC

  • Major Operation between ESME and SMSC

The major operation between ESME and SMSC are:

  1. Bind operation
  2. Unbind operation
  3. Submit_SM operation
  4. Deliver_SM operation

Bind operation is carried out to connect ESME server and SMSC server. Unbind Operation is carried out to release connection between ESEM server and SMSC server. Submit_SM and Deliver_SM are operation carried out to send and deliver short message between ESME and SMSC server. There are two types of bind operation:

  1. Bind_Transmitter
  2. Bind_Receiver

All these operation process is explained below with figure.

The figure below illustrates the process of bind_transmitter operation between ESME and SMSC servers.

Bind Process between ESME and SMSC servers

Fig: Bind_Transmitter (Bind Process between ESME and SMSC servers)

The figure below illustrates the process of bind_receiver operation between ESME and SMSC servers.

Bind_Receiver Process

Fig: Bind_Receiver Process between ESME and SMSC

The figure below illustrates the communication process between ESME server and SMSC server for transmitting and receiving Short Messages

 

Short Message transfer between ESME and SMSC

Fig: Short Message transfer between ESME and SMSC

Thus mobile user sends sms to ESME and is then send to by that ESME to the SMSC server and the bill is generated by counting the number of SMS send or received. The SMS count for each ESME account is identfied by the SMS short code given at the time of interconnection of the ESME and SMSC. The amount per SMS is subject to business policy between the two SMS service provider.

Thus the design of ESME involves the software support of the above feature.

 
]]> http://blog.ektel.com.np/2012/01/sms-messages-between-esme-server-and-smsc-server/feed/ 0